Cisco Technology, Inc.

Eigenix

Headway Technologies, Incorporated

Sung Soo Chung

Sang Hyeon Baeg

Min Li

Kowang Liu

Chen-Jung Chien

Min Zheng

David Hu

David M Drouin

Xinli Gu

Hongshin Jun

Hong-Shin Jun

Heong Kim

Frank Tsang

The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.

Method and apparatus for fault injection

The resonance frequency of a forced torsionally oscillating mirror MEMS device can be controlled in the presence of perturbations by means of a closed loop feedback device and method of using it. The method is implemented through a simple algorithm, implemented in either software or hardware, that maintains the condition of resonance, or another selected frequency, by recursively determining that the center of the driving voltage pulse is positioned at a point on the measured positional waveform of the oscillating system.

Drive method for starting and operating a resonant scanning MEMS device at its resonant frequency

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Apparatus and system for implementing variable speed scan testing

Methods for implementing variable speed scan testing

A dynamic fly heater (DFH) for improved lifetime and better film uniformity is disclosed for a magnetic head. The heater has a lower amorphous Ta layer and an upper W layer to promote small grain size and reduced electro-migration. The composite film is especially advantageous for heaters greater than 1000 Angstroms thick where dR/R is difficult to control in the prior art. The DFH may be a (Ta/W)laminate in which the Ta layers are about 30 Angstroms thick and the combined thickness of the W layers is from 400 to 1200 Angstroms. A Ta film is preferably sputter deposited with an Ar pressure of 3 to 5 mTorr and the W film is sputter deposited in the same chamber with a 3 to 20 mTorr Ar pressure. In one embodiment, a merged read/write head has one DFH in the read head and a second DFH in the write head.

Ta/W film as heating device for dynamic fly height adjustment

A method, involving: inputting an initial data pattern into a scan chain circuit of an integrated circuit device; applying a particle beam to the integrated circuit device, while driving the scan chain circuit with a clock signal, to generate an output data pattern; and generating a single event upset error rate test result based on a comparison between the output data pattern and the initial data pattern.

Single event upset test circuit and methodology

A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.

Programmable in-situ delay fault test clock generator

A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test

An AC boundary scan cell is disclosed. For one embodiment the AC boundary scan cell includes a first multiplexer, a second multiplexer, a first data shift register, a second data register, an XOR logic gate, and a third multiplexer. For one such embodiment the AC boundary scan cell includes an SDI line, an SDO line, a TDI line, a TDO line, a ShiftDR signal input line, an AC_Pattern_Clock or ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. The AC boundary scan cell also includes an AC_Pattern_Source signal input line and an AC_Test signal input line. For one such embodiment, each line is coupled to receive the corresponding signal from the boundary scan logic.

AC coupled line testing using boundary scan test methodology

Testing AC coupled interconnects using boundary scan test methodology. Specially designed AC boundary scan cells and boundary scan logic are used. These are compatible with IEEE Standard 1149.1 testing. An AC_EXTEST method is used to determine the reliability of the AC coupled interconnections. The method includes preloading the test stimulus, initiating the AC_EXTEST instruction, executing the instruction, transferring the instruction results, and evaluating the results. During the test, the TAP controllers of both the driving and receiving ICs are held in the Run-Test/Idle state for the time required to complete execution of the instruction. During this time, the driving IC is applying the AC test stimulus to the interconnections and the receiving IC is sampling the signal. The test may be repeated with different test data and may be run together with a DC EXTEST method to determine the reliability of both the AC and the DC coupled interconnections independently.

Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.

Programmable test pattern and capture mechanism for boundary scan

Resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit includes analyzing a circuit path-list corresponding to the integrated circuit for timing violations and generating a circuit timing violations analysis output; generating a first LBIST/circuit path-list based on the circuit path-list and an LBIST path-list corresponding to the LBIST sub-circuit; analyzing the first LBIST/circuit path-list for timing violations and generating an LBIST/circuit timing violations analysis output; comparing the LBIST/circuit timing violations analysis output with the circuit timing violations analysis output; generating an LBIST/circuit constraint file based on the comparison and predetermined protocols; and generating a second LBIST/circuit path-list based on the circuit path-list, the LBIST path-list and the constraints file. In this way, timing problems are quickly and efficiently resolved.

Resolving LBIST timing violations

A mechanism for enabling compliance with the IEEE boundary-scan standard 1149.1 includes, in a first preferred embodiment, a compliance enabler working with non-compliant embedded boundary-scan cells to enable a Device Under Test (DUT) to function as an IEEE-standard-compliant part, thus allowing full utilization of existing test tool generation and operation of the IEEE standard. The enabler is preferably provided separately from boundary scan-cells embedded in core logic designs. The enabler includes a Test Access Port (TAP) controller and related decoding circuits to generate necessary compliance signals based on various conventional TAP controller variables and instruction functions. The embedded boundary-scan cells preferably include an internal scan cell architecture. In a second embodiment, a second enabler works with a TAP emulator to allow testing of TAP-less DUTs.

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San Jose, CA, United States of America

Sung Soo Chung