Intel Corporation

Sung Soo Cho

James P Kardach

Jayesh M Joshi

Nicholas B Peterson

Thomas R Lane

Gregory Scott Mathews

Neil W Songer

Cau L Nguyen

Kameswaran Sivamani

Edward S Zager

David S Vannier

Nima Homayoun

Shing Wong

David I Poisner

Eugene P Matter

Deepak Tripathi

A system includes a portable computer having a first bus and a docking base having a second bus. A serial link (e.g., a 1394 link) couples the portable computer to the docking base. The portable computer may include a controller to convert a first bus cycle targeted for the second bus to a serial cycle. The first and second buses may each include a Peripheral Component Interconnect (PCI) bus.

Docking system

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

Serial interrupt bus protocol

A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop. If the graphics controller is in a low power or 'sleep' state, the AGP bus clock CLK is stopped, thereby conserving power.

Method and apparatus for stopping a bus clock while there are no

A method and apparatus for indicating when a device in a computer system is communicating with memory. Information is communicated between the device and memory in a manner that bypasses a bus. A side-band signal that indicates that this communication is transpiring is sent to a second device connected to the second bus. In response to this side-band signal, a bit in a register of the second device is set to a value that is then communicated by way of the second bus.

Method and apparatus for indication when a bus master is communicating

A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.

Method and apparatus for selectively invoking a particular interrupt

A computer system having switchable 3.3 volt or 5 volt interface bus. The computer system includes a microprocessor and multiple peripheral integrated circuits. The microprocessor and other peripheral integrated circuits are coupled to the interface bus through groups of buffers on the integrated circuits. These buffers operate at the voltage level of the interface bus and include voltage translation circuitry for translating interface bus signals to voltage level at which the core logic of the microprocessor and other peripheral chips operate.

Method and apparatus for interfacing a bus that operates at a plurality

A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.

Method and apparatus for interrupt signaling in a computer system

A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

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Sunnyvale, CA, United States of America

Sung Soo Cho