Intel Corporation

Sung-Soo Cho

James P Kardach

Debra T Cohen

Diane M Bryant

Neil W Songer

John William Horigan

David I Poisner

Feng Deng

Satchit Jain

Chao-Hsin Chi

Jim S Cheng

Seyed Yahay Sotoudeh

David Chang

Chandrashekar M Reddy

Nader Raygani

Nikhil Mazumder

Steven M Farrer

Meeling Roberts

Farid Rastgar

Pranav S Shah

Scott D Hirose

A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Method of initializing a memory controller by executing software in a second memory to wake up a system

Initializing a memory controller by executing software in second memory to wakeup a system

The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal line, and two agents coupled to the bus and the third signal line. The first agent claims to be a target of a transaction on the bus without decoding the address associated with the transaction by asserting the first signal on the first signal line. The second agent responds to the transaction as the target. The second agent thereafter asserts a third signal on the third signal line to coordinate deassertion of the first signal on the first signal line by the first agent and concurrent assertion of the second signal on the second signal line by the second agent.

Method and apparatus for splitting a bus target response between two

Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the complexity, weight, and power consumption of the notebook computer. The present invention provides for a method for quiet docking and undocking of a notebook computer using interface circuitry located within the docking station. Moreover, the method of the present invention provides for docking and undocking whether the notebook computer is in a powered-on or suspend mode. The notebook computer is docked and undocked to the docking station such that any transaction occurring on the system bus during the docking/undocking sequence is not affected.

Method and apparatus for docking and undocking a notebook computer to

Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

Method and apparatus for docking and undocking a notebook computer

A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.

Method and apparatus for handling bus master and direct memory access

A system having a portable computer, a docking station and an interface coupled between the portable computer and the docking station that is responsive to unpreconditioned insertion or removal of the portable computer into or from the docking station respectively. When the portable computer is being inserted into or removed from the docking station, the interface generates events to allow software to configure (e.g., precondition) the portable computer and the docking station without prior user intervention.

Method and apparatus for automatic un-preconditioned insertion/removal

A computer system has a first bus, a first bus bridge, and a second bus bridge. The first bridge connects the first bus to a second bus and the second bridge connects the first bus to a third bus. Normally, the first bridge behaves as the only subtractive decode agent on the first bus, claiming all transactions initiated on the first bus that target agents on the second bus or the third bus. If the first bridge claims a transaction targetting an agent on the third bus, the first bridge transfers the responsibility to respond to the transaction to the second bridge. The first bridge does not behave as the subtractive decode agent on the first bus when transactions are initiated on the second bus and forwarded to the first bus. In that case, the second bridge behaves as the subtractive decode agent on the first bus.

Method and apparatus for supporting two subtractive decode agents on the

A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.

Input output controller having interface logic coupled to DMA controller

Method and apparatus for handling bus master channel and direct memory

A high speed bus for communicating between a processing component and a display component of a computer. The high speed bus substantially enhances video graphics application performance by allowing the process component and the display component to communicate without using the system bus. By coupling the processing component and the display component via a high speed bus, video graphics instructions may be routed directly from the processing component to the display component, thereby eliminating the delay associated with the slower standard system bus lines. By using the high speed bus, the processing component is able to communicate with the display component without having to place instructions onto the busier system bus.

Method for implementing a high speed computer graphics bus

A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

Slow memory refresh in a computer with a limited supply of power

In an integrated circuit comprising discrete circuit modules, dedicated test signals for the individual circuit modules are multiplexed with operational signals to the external pins of the integrated circuit. When not in a test mode, the external pins of the chip are coupled to the normal operational signals. When a test mode is commanded, certain external pins are coupled to test signals that are not otherwise available off-chip in accordance with the contents of a test register.

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Sunnyvale, CA, United States of America

Sung-Soo Cho