Skhynix Inc.

Sung Soo Chi

Jae Hwan Seo

Sung Yub Lee

Min Soo Park

Sang Hyun Ku

Ja Beom Koo

Jun Cheol Park

Sang Kyung Shin

Dong Woo Lyu

Jin Yo Park

Kwang Soo Ahn

Sung Su Cha

A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

Semiconductor apparatus

A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.

Pulse width compensation circuit and a semiconductor apparatus using the pulse width compensation circuit

A semiconductor device is disclosed. The semiconductor device includes a first cell array and a second cell array, a first main word line disposed over the first cell array, a second main word line disposed over the second cell array, and a row decoder block disposed between the first cell array and the second cell array, and configured to include a common signal line that is commonly coupled to the first main word line and the second main word line such that a main word line control signal is simultaneously supplied to the first main word line and the second main word line.

Semiconductor device

A semiconductor device includes a cell array having an upper segment and a lower segment which are classified according to refresh units. The semiconductor device includes a first repair controller configured to output a first repair signal for controlling a repair operation of the upper segment based on a fuse address, a row address, a second control signal, and selection address being at a first level, and generate a first control signal for controlling a repair operation of the lower segment based on the fuse address, the row address, and selection address.

Semiconductor device with array configuration including upper segment, lower segment classified according to refresh units, repair controllers for controlling repair operation of upper segment and lower segment

A semiconductor device is disclosed, which is configured to perform a test using various conditions during a test mode. The semiconductor device includes a voltage generation circuit configured to output 2(n is an integer of n&#x2265;2) bit-line precharge voltages through different power-supply lines, based on a mode control signal, and a sense amplifier configured to receive the bit-line precharge voltages from the voltage generation circuit, and supply the 2bit-line precharge voltages to corresponding bit lines in units of 2successive bit-lines within the same cell array.

A semiconductor apparatus includes a state storage circuit configured to store information depending on a plurality of signals, and output the stored information as a power gating signal. The semiconductor apparatus may include a power gating circuit configured to provide or block a power supply voltage to an internal operation circuit as a driving voltage in response to the power gating signal.

The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. The semiconductor device may include a current path control unit configured to increase the speed at which the voltage of the main word line signal decreases.

Semiconductor device with current path control unit for decreasing the level of a voltage

A semiconductor device may be provided. The semiconductor device may be configured for detecting a defect of a fuse set. The semiconductor device may include a pseudo initial signal generator configured to generate pseudo initial information on the basis of a test mode signal. The semiconductor device may include a fuse-set defect detector configured to compare fuse-set information of a fuse set or the pseudo initial information with a reference value on the basis of a fuse-set address, and detect a defect of the fuse set.

Disclosed is a driving test circuit including a driving circuit that drives a sub-word line based on a first voltage and a driving signal, and a test element circuit that adds a resistance component between the driving circuit and the first voltage based on a test mode signal.

Driving test circuit and semiconductor device including the same

A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a latch set configured to latch the boot-up data when a latch select signal is activated in the boot-up operation, and output data latched as the latch select signal is activated as a repair column address in a normal operation.

Latch circuit and semiconductor device including the same

A data input/output circuit includes a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed; and a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first inverted input/output line by the second internal voltage when the active operation is performed.

Growing community of inventors

Yongin-si, South Korea

Sung Soo Chi