Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Hanyang University

Soongsil University

Sung-Rae Kim

Jun Jin Kong

Ki Jun Lee

Jin-Hoon Jang

Kijun Lee

Sunghye Cho

Myungkyu Lee

Dong-Joon Shin

Myung Kyu Lee

Yeong Geol Song

Hong Rak Son

Jun-Jin Kong

Hong-Rak Son

Jaeyoun Youn

Yeonggeol Song

Yesin Ryu

Beom Kyu Shin

Ki-Jun Lee

Chanki Kim

Hyung-June Kim

Heon Hwa Cheong

Isak Hwang

Sung-Han Jung

Gyu Yeol Kong

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Memory device and memory system including the same

Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit

A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

Memory device and method reading data

A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

Decoder using low-density parity-check code and memory controller including the same

Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.

LDPC encoding/decoding method and device using same

An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits.

Encoding device, controller and system including the same

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Seoul, South Korea

Sung-Rae Kim