Samsung Electronics Co., Ltd.

K-mac

Osong Medical Innovation Foundation, Korea University Research and Business Foundation

Sugentech, Inc.

Sung-Min Seo

Sang-Joon Hwang

Je-Min Ryu

Ho-Young Song

Kyo-Min Sohn

Sang-Bo Lee

Nak-Won Heo

Jong-Min Oh

Yun-Young Lee

Gil-Su Kim

Kyu-Hyoun Kim

Chul-Soo Kim

Ju-Seop Park

Su-Jin Ku

Je-Min Yu

Mun-Cheol Paek

Jin-kyoung Jung

Joong Hwan Lee

Jae-Young Lee

Seong-Jin Jang

Jun-Hyung Kim

Hyoung-Joo Kim

Jong-Pil Son

Yong-Ho Cho

Myeong-O Kim

Se-Hwan Paek

Chi-Wook Kim

Sin-Ho Kim

Do-Bu Lee

Jae-Hyung Park

Oleksandrov Sergiy

Chi Wook Kim

Sergiy Oleksandrov

Disclosed is a method of synthesizing a polymeric fluorescent tracer for signal amplification, including (a) subjecting a streptavidin-fluorophore conjugate (SA-FL) and a spacer-attached biotin-conjugated antibody (b-Ab) to reaction at least two times; (b) treating a dual biotin oligomer spacer (db-oN); and (c) performing a homogenization process.

Method of synthesizing polymeric fluorescent tracer for signal amplification

A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Semiconductor memory devices including redundancy memory cells

Provided are a system for integrated analysis of a real-time polymerase chain reaction and a DNA chip and a method for integrated analysis using the same, and more particularly to an apparatus for integrated analysis of a real-time polymerase chain reaction and a DNA chip and a method for integrated analysis using the same. According to the method for integrated analysis of a biomaterial of the present invention, gene amplification proceeds and subsequently hybridization proceeds in a single reactor, thereby preventing contamination of the sample due to external factors, which may be caused while the sample is transferred for reaction, and automating a series of procedures such as injection of the sample, reaction of the biomaterial, and detection and analysis of results.

System for integrated analysis of real-time polymerase chain reaction and DNA chip and method for integrated analysis using the same

A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Fuse data reading circuit having multiple reading modes and related devices, systems and methods

Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Semiconductor memory device having OTP cell array

A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Semiconductor memory device including sensing verification unit

A data read start decision device includes: a storing circuit configured to store code key data; a read check circuit configured to output a read start signal in response to code key data read from the storing circuit, and a controller configured to start reading environment setting data from the storing circuit in response to the read start signal. The read check circuit is configured to at least one of: receive the read start signal from the controller and transfer the read start signal to the controller in response to the read code key data; and generate the read start signal based on the read code key data and output the read start signal to the controller.

Devices and methods for deciding data read start

A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Memory device, method of operating the same, and electronic device having the memory device

Provided is a biomaterial detecting device for confirming or detecting a biomaterial reaction, and more particularly to a biomaterial detecting device, which is formed in a stick type to thereby be immersed in a tube containing a biomaterial solution to be tested; has an upper portion with a cap structure to thereby induce reaction with a biomaterial, and thus facilitate confirmation and detection of the biomaterial; and is formed in a cap structure to thereby prevent evaporation of a sample and infiltration of an external material at the time of a biomaterial reaction in the tube, and thus improve reliability in analysis.

Biomaterial detecting device

For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled.

Method of selecting anti-fuses and method of monitoring anti-fuses

A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.

Redundancy repair circuit and a redundancy repair method therefor

Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits

Semiconductor memory devices include a memory cell array region having a plurality of memory cells, a local data I/O line pair that is electrically connected to the plurality of memory cells, a local sense amplifier that is electrically connected to the local data I/O line pair, a read global data I/O line pair that is electrically connected to the local sense amplifier and that is configured to transmit data during a read operation and a write global data I/O line pair that is electrically connected to the local sense amplifier that is configured to transmit data during a write operation.

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Seoul, South Korea

Sung-Min Seo