Samsung Electronics Co., Ltd.

Ness Capacitor Co., Ltd.

Nesscap Co., Ltd.

Sung-min Kim

Eun-jung Yun

Dong-Gun Park

Jeong-Dong Choe

Chang-Sub Lee

Seong-Ho Kim

Shin-Ae Lee

Dong-Won Kim

Sung-Dae Suk

Sung-young Lee

Dong-won Kim

Sung-Young Lee

Du-Eung Kim

Beak-Hyung Cho

Kyu-Seok Kim

Jae-Man Yoon

Sang-Woo Kim

Min-sang Kim

Byung-seo Kim

Jong-Soo Seo

Ming Li

Yong-Ho Jung

Eun-Sil Kim

Sung-Chul Park

Seung-nam Cha

Kyoung-hwan Yeo

Young-Bee Chu

Jeong-Seok Oh

Ha-Young Lee

Jeung-Soo Kim

Ho-Jung Lee

Heui-Soo Kim

Sung-chul Park

Hee-Young Lee

Jung-Inn Sohn

Seung-Nam Cha

Ju-Seok Seo

According to an example embodiment, an electrical energy generator includes at least one piezoelectric structure, a semiconductor layer and a contact layer. The at least one piezoelectric structure includes a material having piezoelectric characteristics. One surface of each piezoelectric structure forms a p-n junction with the semiconductor layer. The other end of each piezoelectric structure contacts the contact layer that is formed of a material having metal-insulator transition (MIT) characteristics. The piezoelectric structure may be an elongated member, such as a nanowire.

Electrical energy generator

In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell

Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

Gate-all-around integrated circuit devices

A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

Semiconductor device with FinFET and method of fabricating the same

A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Methods of fabricating semiconductor devices with enlarged recessed gate electrodes

The present invention relates to a display device having a panel assembly that includes first and second display panels arranged to face each other. The second display panel is smaller than the first display panel. The first display panel and the second display panel are divided into a front display area and a rear display area to display images on both sides of the panel assembly.

Dual sided liquid crystal display device viewable from one side in a reflection mode and the other side in a transmission mode

A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

MOS field effect transistor having plurality of channels

A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

An apparatus for dual display includes a light unit providing a light and a display panel. The display panel includes a transmissive pixel transmitting the light from the light unit and a reflective pixel reflecting the light from the light unit. The display panel displays a first image on one side of the light unit by using the light transmitted by the transmissive pixel, and displays a second image on an opposite side of the light unit by using the light reflected by the reflective pixel. The display panel includes a first substrate, a second substrate combined with the first substrate and disposed adjacent to the light unit, and a liquid crystal layer interposed between the first and the second substrates. The display panel further includes a reflective layer formed on the first substrate corresponding to the reflective pixel. Therefore, a total thickness of the apparatus for dual display can be reduced considerably by using the light unit as a second display screen.

Dual display apparatus

In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

3-Dimensional flash memory device and method of fabricating the same

Disclosed are an electric energy storage device having a good cycle characteristic and a temperature characteristic and a method of charging and discharging the electric energy storage device. The electric energy storage device including a capacitor and a secondary battery combined in series is provided. When the capacitor of the electric energy storage device is an electric double layer capacitor, the capacitor is used to the voltage of OV or less to increase an available energy usage.

Electric energy storage device and method of charging and discharging the same

Method of fabricating a MOS field effect transistor having plurality of channels

A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

Semiconductor device with multiple channels

Semiconductor devices with enlarged recessed gate electrodes

MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

MOS Transistors having inverted T-shaped gate electrodes and fabrication methods thereof

Growing community of inventors

Incheon Metropolitan, South Korea

Sung-min Kim