Samsung Electronics Co., Ltd.

Sung-Min Joe

Sang Soo Park

Kang-Bin Lee

Seung-Jae Lee

Sun-gun Lee

Chung-Ho Yu

A memory device includes a substrate, a first cell string, second cell string, and third cell string, each connected to a first bit line and formed in a direction perpendicular to a top surface of the substrate, a first upper ground selection line connected to the first cell string, a second upper ground selection line separated from the first upper ground selection line and connected to the second and third cell strings, a first lower ground selection line connected to the first and second cell strings, and a second lower ground selection line separated from the first lower ground selection line and connected to the third cell string.

Memory device including asymmetric ground selection lines

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

Memory device with improved program performance and method of operating the same

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

Nonvolatile memory device including a logic circuit to control word line voltages

A nonvolatile memory device includes a memory cell array, a voltage generator and a control logic circuit for programming a selected memory cell of the memory cell array to a selected word line into a first program state by controlling the voltage generator and a verify operation on the memory cell array. The control logic circuit controls a first word line voltage applied to an adjacent word line not to be programmed in the verify operation to be different from a read voltage level of a read voltage applied in a read operation of the nonvolatile memory and controls a bit line voltage applied to a bit line in the read operation. The control logic circuit controls the voltage generator to apply a plurality of different and decreasing verify voltages to the selected word line in the verify operation.

Nonvolatile memory device including a logic circuit to control word and bitline voltages

Nonvolatile memory device including a verify circuit to control word and bit line voltages and method of operating the same

A nonvolatile memory device includes a verify circuit, in a peripheral circuit region, controlling a verify operation by controlling a word line voltage applied to at least one unselected word line not to be programmed and a bit line voltage applied to a bit line connected differently from a voltage applied in a read operation. The at least one unselected word line includes a first word line located directly above a selected word line to be programmed and a second word line located directly below the selected word line. The verify circuit applies a word line voltage to the first word line and applies the same word line voltage to the second word line in the verify operation. The word line voltage has a different voltage level than a read voltage applied to the first word line and the second word line in a read operation.

Non-volatile memory device including a verify circuit to control word and bit line voltages and method of operating the same

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.

A method of programming a non-volatile memory device including a first memory block and a second memory block includes: performing a first program operation on a first memory cell in the first memory block and connected to a first word line of a first level with respect to a substrate; after the performing of the first program operation on the first memory cell, performing the first program operation on a second memory cell in the second memory block and connected to a second word line of the first level; and after the performing of the first program operation on the second memory cell, performing a second program operation on the first memory cell.

Nonvolatile memory device and a method of programming the nonvolatile memory device

A method of operating a memory device includes performing a first program operation on memory cells connected to a first word line among a plurality of word lines, performing the first program operation on memory cells connected to a second word line among the plurality of word lines, applying a turn-on voltage at a first level to the first and second word lines, applying a voltage at a level lower than the first level to a third word line among the plurality of word lines, performing a precharge operation on partial cell strings among a plurality of cell strings, and performing a second program operation on the memory cells connected to the first word line.

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Seoul, South Korea

Sung-Min Joe