Samsung Electronics Co., Ltd.

Lg Chem, Ltd

Korea Institute of Science and Technology

Sung-Min Hwang

Joon-Sung Lim

Han-Soo Kim

Jang-Gn Yun

Hansoo Kim

Wonseok Cho

Won-Seok Cho

Jae Ho Ahn

Suk Kang Sung

Jaehoon Jang

Woon-Kyung Lee

Jae-Hoon Jang

Ji Won Kim

Sun-Il Shim

Dong-Sik Lee

Jae-Joo Shim

Jiwon Kim

Woosung Yang

Zhiliang Xia

Eunsuk Cho

Se-Jun Park

Ahn-Sik Moon

Hyang Mok Lee

Chang Bum Ahn

Woonkyung Lee

Ki-Hyun Kim

Jiyoung Kim

Jae-Hun Jeong

Hoosung Cho

Byungjin Choi

Jihoon Cho

Hyun-Chul Jung

Oh Young Hyun

Hui-Chang Moon

Jihye Kim

Sang Don Lee

Kyoung-Hoon Kim

Sukkang Sung

Hyeong Jin Kim

Ju-Young Lim

Ki Hong Min

Wooyong Lee

Changmin Han

Sang Hyuck Park

Byeong Geun Kim

Bum Kyu Kang

Gilsung Lee

Dong-Myung Kim

Ji-Young Kim

Ji Young Kim

Jung-Hwan Kim

Han-soo Kim

Kang-Won Lee

Changhyun Lee

Dae-seok Byeon

Sang-Seok Kang

Byoungkeun Son

Sunghoi Hur

Sunyoung Kim

Jun Hwan Jang

Jintaek Park

Young-Ho Lee

Sungjin Kwon

Kiwoong Kim

Ji-Won Kim

Cha-Hun Ku

Hyung Ku Yun

Do-Gyun Kim

Sung-Jong Kim

Jae-hoon Jang

Ho-Sung Song

Jongwon Kim

Jaesun Yun

Jong-Sun Kim

Won-seok Cho

Seong-Soon Cho

Young-Ju Park

Changseok Kang

Jae-woong Lee

Ju-Hwan Baek

Soo Min Park

Jaeho Ahn

Hyang-Mok Lee

Byungjin Lee

Han Sung Lee

Ki Hun Song

Jung Kyu Woo

Sunghyun Kim

Su Taek Jung

Jee-Yong Kim

Choong-sun Shin

Dongmyung Kim

Jong-Yeon Kim

Tae Il Kim

Woo Sung Yang

Jae Hoon You

Woo-Sung Yang

Yong-Su Choi

Sanggon Kim

Byung Taek Yang

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

Semiconductor device and electronic system including the same

A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

Nonvolatile memory device

A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

Nonvolatile memory device, system including the same and method of fabricating the same

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Vertical memory devices and methods of manufacturing the same

A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

Semiconductor memory devices and methods of fabricating the same

A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Semiconductor memory device

A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Three-dimensional semiconductor memory device and method of fabricating the same

A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

Semiconductor memory device and electronic system including the same

A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

Nonvolatile memory device and method for fabricating the same

The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

Nonvolatile memory device and nonvolatile memory system including the same

A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

Semiconductor memory device, electronic system including the same, and method for fabricating the same

A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and the second block.

Three-dimensional semiconductor memory device

Growing community of inventors

Seoul, South Korea

Sung-Min Hwang