Samsung Electronics Co., Ltd.

Sung-Min Hong

Bub-chul Jeong

Jae Geun Yun

Jaegeun Yun

Jong Ho Roh

Hyun-Joon Kang

Joon-Woo Cho

Woo-Hyung Chun

Junhyung Um

Il Han Park

Young-Seok Kim

Tae-Kyung Kim

Jong-Jin Lee

Sung-Jae Lee

Woosung Choi

Sung-Bin Hong

Jae-Geun Yun

Seong-Min Jo

Eun-Ok Jo

Min-Je Jun

Jinyong Jung

Hyunuk Jung

Woo Cheol Kwon

Eui-Cheol Lim

Jae-Young Hur

Sim Ji Lee

JaeYoung Hur

JiWoong Kwon

Jung-Sik Lee

Ling Ling Liao

Sunghoon Shim

Sim-Ji Lee

According to various examples of the present invention, an electronic device and a gaze tracking method of the electronic device: detect optical signals, which are outputted from a first light-emitting device and a second light-emitting device and reflected from a user's left eye and right eye, by means of a first camera and a second camera corresponding to each of the first light-emitting device and the second light-emitting device; and determine the user's gaze on the basis of the detected optical signals, wherein the first light-emitting device and the second light-emitting device can be positioned so as to correspond to a left-eye display region and a right-eye display region included in a display of the electronic device, respectively, and various other examples are also possible.

Electronic device and gaze tracking method of electronic device

A computing system includes a processor that operates a plurality of virtual machines in which a plurality of operating systems are respectively executed. The processor executes a hypervisor that groups the plurality of virtual machines into a normal virtual machine group and a privilege virtual machine group, and that controls hardware accesses requested by the normal virtual machine group and the privilege virtual machine group. The processor executes a normal application in the normal virtual machine group, and executes a secure application in the privilege virtual machine group.

Computing system for securely executing a secure application in a rich execution environment

A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address.

Semiconductor device including a content firewall unit that has a secure function

Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

System interconnection of system-on-chip

A page descriptor can be stored in advance in a memory management unit under various conditions so that an address translation overhead can be reduced. The memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer (TLB) stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor corresponding to a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor corresponding to the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor corresponding to the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor corresponding to the received virtual address; and performs a translation of the virtual address to a physical address using the page descriptor corresponding to the received virtual address. The prefetch buffer may include sub-prefetch buffers, and may be updated based on access direction information.

System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer

Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Interconnect, bus system with interconnect and bus system operating method

A bus system of a system on chip (SoC) includes a first and a second masters, a first slave, and a first and a second control modules. The control modules generates a first and a second access control state signals in response to a first locking access preparation request signal from a corresponding master. The access control signals are broadcasted between the first and the second control modules through a communication channel. A method of operating a bus system in a locked access mode includes allowing one of masters to access one of slaves through a control module and restricting other masters from accessing the one of slaves through other control modules connecting the other masters and the one of slaves in accordance with a control state signal.

System on chip bus system and a method of operating the bus system

A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.

Memory interleaving device to re-order messages from slave IPS and a method of using a reorder buffer to re-order messages from slave IPS

A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.

System on chip comprising interconnector and control method thereof

A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

System-on-chip and data arbitration method thereof

A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include: a first select-gate structure and a second select-gate structure disposed on the cell region, the first select-gate structure and the second select-gate structure spaced apart from each other, and a plurality of cell gate structures disposed between the first select-gate structure and the second select-gate structure. At least one of the select-gate structures comprises plural select gates.

Semiconductor memory device and method of fabrication and operation

Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

Bandwidth synchronization circuit and bandwidth synchronization method

An apparatus and a method for preventing power consumption in a multi-mode portable terminal are provided. The apparatus includes a first communicator communicating with a mobile communication network; a second communicator communicating with a heterogeneous network; and a controller controlling the second communicator to scan an Access Point (AP) so as to perform a service connection to the heterogeneous network if a service connection to the mobile communication network is performed through the first communicator.

Apparatus and method for preventing power consumption in multi-mode portable terminal

A method and system for detecting a state of a disc drive. A cable select signal is input from a host and is gated to determine the state of the disc drive when a jumper is set to indicate that the disc drive is in a cable select state or when the jumper is missing. The cable select signal is prevented from determining the state of the disc drive when the jumper is present and is set to indicate that the disc drive is in the master state or the slave state. Additionally, the cable select signal dictates the state of the disc drive when the jumper is present and is set to indicate that the disc drive is in the cable select state.

Growing community of inventors

Hwaseong-si, South Korea

Sung-Min Hong