Samsung Electronics Co., Ltd.

Sung-man Whang

Dong-won Kim

Hyung-Moo Park

Hyae-Ryoung Lee

Chang-woo Noh

Han-su Oh

Dong-cho Maeng

Ho-woo Park

Mun-hyeon Kim

An integrated circuit device includes a base burying insulating film covering a lower side wall of a fin-type active region on a substrate, an isolation pattern having a top surface higher than a top surface of the base burying insulating film, and a gate line covering a channel section of the fin-type active region. The gate line has an upper gate covering an upper portion of the channel section and a lower gate protruding from the upper gate toward the substrate and filling a space between a lower side wall of the channel section and an upper side wall of the isolation pattern.

Integrated circuit device

In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.

Method of fabricating metal oxide semiconductor transistor with lightly doped impurity regions formed after removing spacers used for defining higher density impurity regions

Growing community of inventors

Yongin-si, South Korea

Sung-man Whang