Samsung Electronics Co., Ltd.

Sungkyunkwan University

Sung Man Whang

Myung Gil Kang

Woo Cheol Shin

Sadaaki Masuoka

Sang Hoon Lee

Tae Jin Park

Sang Woo Lee

Jin Bum Kim

Kwan Heum Lee

Munhyeon Kim

Yong Hee Park

Keon Yong Cheon

Chang Woo Noh

Si Hyung Lee

Hong Bae Park

Sang Hoon Baek

Hyoung Sub Kim

Seung Han Park

Sang Hoo Lee

Maria Toledano Lu Que

A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Semiconductor device having a plurality of channel layers and method of manufacturing the same

A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

Semiconductor device including non-sacrificial gate spacers and method of fabricating the same

Method of manufacturing semiconductor device having a plurality of channel layers

A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.

Vertical field effect transistor having an elongated channel

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Hwaseong-si, South Korea

Sung Man Whang