Skhynix Inc.

Sung-Lae Oh

Soo-Nam Jung

Dong-Hyuk Kim

Jin-Ho Kim

Chang-Man Son

Go-Hyun Lee

Tae-Sung Park

Sang-Hyun Sung

Chang-Woon Choi

Young-Ock Hong

Jung-Mi Tak

Jung-Hoon Lee

Ji-Eun Joo

Je-Hyun Choi

Ji-Hyun Choi

Kwang-Hwi Park

Seong-Hun Jung

A semiconductor memory device includes a first stack including a plurality of conductive layers and a plurality of first interlayer insulating layers alternately stacked on a substrate; a second stack including a plurality of sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the substrate; a plurality of stepped grooves defined at different depths in the first stack; and an opening defined in the second stack, and having, on a sidewall thereof, a plurality of steps which have the same heights as differences in depth between the plurality of stepped grooves.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Semiconductor memory device with 3D structure

A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

Semiconductor memory device of three-dimensional structure

A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.

Semiconductor device

A semiconductor memory device includes a cell wafer including a first plane and a second plane which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells; and a peripheral wafer including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively. The cell wafer includes, on one surface thereof bonded to the peripheral wafer, a first pad which is coupled in common with the first plane and the second plane, and the peripheral wafer includes, on one surface thereof bonded to the cell wafer, a second pad which is coupled with the row decoder and is bonded to the first pad.

Semiconductor memory device

A semiconductor memory device includes a substrate defined with a cell array region and a connection region which extends in a first direction from the cell array region; an electrode structure including a bottom electrode structure which includes plurality of bottom electrodes stacked on the substrate to be separated from one another and a top electrode structure which includes plurality of top electrodes stacked on the bottom electrode structure to be separated from one another and has a stepped structure which includes plurality of stepping surfaces, in the connection region; and plurality of recess holes formed to a first depth from stepping surfaces of the stepped structure, and having bottom surfaces which expose the bottom electrode structure, wherein the first depth is substantially same as a height of the top electrode structure, and distances of the bottom surfaces of the recess holes from the substrate are different from one another.

A memory device includes a plurality of bit lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein the page buffer circuit is divided into a plurality of page buffer regions and is laid out at both sides of the cache circuit in the first direction.

Memory device

A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.

A semiconductor memory device includes gate lines and wiring lines which are stacked over a substrate. The gate lines are stacked over first and second cell array regions of a substrate which are disposed in a second direction crossing with a first direction, and are passed through by channel structures. The wiring lines are stacked over an interval region of the substrate which is disposed between the first and second cell array regions and over first coupling regions of the substrate which are disposed at both sides of the first and second cell array regions and the interval region in the first direction. Each of the wiring lines includes a line portion which traverses the interval region in the first direction and extended portions which are disposed over the first coupling regions. A width of the extended portions is larger than a width of the line portion.

A semiconductor memory device comprises a memory cell array disposed on a substrate, a plurality of bit lines disposed on the a memory cell array, each bit line extending in a first direction parallel to the top surface of the substrate and divided into a first bit line section and a second bit line section, and a plurality of source line pads disposed at the same layer as the bit lines between the first bit line sections of the bit lines and the second bit line sections of the bit lines.

A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.

Memory device including page buffers

A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.

Growing community of inventors

Chungcheongbuk-do, South Korea

Sung-Lae Oh