Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Sung Kee Park

Ki Seog Kim

Keun Woo Lee

Yoo Nam Jeon

Young Seon You

Hae Sung Park

Keon Soo Shim

Yong Soo Kim

Jin Gwan Shin

Sang Hoan Chang

Yung M Koo

Chung G Choi

Sea C Kim

Sang I Kim

Young I Kim

Yong Wook Kim

Jai O Koh

Il S Hyun

Ho G Ryoo

A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.

Patterns of semiconductor device and method of forming the same

Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures.

Flash memory device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.

Method of fabricating flash memory device

A semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.

Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first dummy active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth.

Flash memory device and method of fabricating the same

Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.

Flash memory cell and method of manufacturing the same and programming/erasing reading method of flash memory cell

The present invention relates to an isolation film in a semiconductor device and method of forming the same.  An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented.

Isolation film in semiconductor device and method of forming the same

The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented.

Method of forming an isolation film in a semiconductor device

A flash memory device and method of manufacturing the same. The flash memory device includes a semiconductor substrate in which a first region where a cell region is formed, a second region where a peripheral region is formed, and a third region formed in the peripheral region at the boundary portion of the cell region and the peripheral region. The device also includes a triple well region formed in the first region and a predetermined region of the third region, an isolation film formed in the first region and having a first depth, an isolation film formed in the second region and having a second depth, which is deeper than the first depth of the isolation film, and a gate oxide film for low voltage and a floating gate, which are stacked on a predetermined region of the first region, a gate oxide film and a gate, which are stacked on a predetermined region of the second region. Additionally, the device includes a dummy flash memory cell in which the floating gate formed in the first region and the gate formed in the second region are separated from each other, and a gate oxide film for high voltage and a gate electrode are stacked on a predetermined region of the third region.

A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.

Row decoder in flash memory and erase method of flash memory cell using the same

Disclosed is a NAND flash memory device which includes butting taps that are formed in such a manner that a poly layer and a silicide layer are connected to given points at the ends of a DSL and the SSL of a NAND flash memory device through a metal contact. The butting taps reduces the resistance of the DSL and the SSL and, consequently, reduce the loading time of the DSL and the SSL.

NAND flash memory device

A well structure in a high voltage device comprises a first well formed in a substrate, the first well having an opposite conductive type from the substrate; a second well isolated from the first well, the second well having the same conductive type as the substrate; a field stop implant region formed between the first well and the second well and spaced apart from each of the first well and the second well by a given distance, the field stop implant region having the same conductive type as the substrate; and a pick-up region overlapped on the field stop implant region, the pick-up region having the same conductive type as the field stop implant region.

Well structure in high voltage device

Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell

The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.

Method of forming a floating gate in a flash memory device

There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.

Growing community of inventors

Icheon-si, South Korea

Sung Kee Park