Au Optronics Corporation

Realtek Semiconductor Inc.

Sung-Kao Liu

Ching-Huan Lin

Hsiang-Lin Lin

Cheng-Yuan Hsiao

Wei-Hung Chuang

Chih-Jen Hu

Chih-Yu Hsu

Yi-Ting Chien

Chih-Ming Chang

Yue-Shih Jeng

Chung-Hsiang Chiu

Shih-Chyuan Fan Jiang

Chun-Hao Lin

Zhen-Ting Huang

Er-Zih Wong

Shih-Chiang Chu

Hung-Tai Chen

Lu Han

Xi-Cheng Shan

Guan-Yu Liu

Lu Xiong

Li He

Chun-Wei Gu

Chia-Yi Chang

Yi-Cheng Tsai

Chi-Rung Wu

Li-Chiao Hung

Yi Cheng Tsai

Po-Hao Chen

Jun-Jiang Huang

A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.

Method for responding to command, storage device and storage system

A command transforming method, applied to a command transforming system comprising a first transceiving interface and a second transceiving interface, comprising: receiving at least one command transmitted from a first device via the first transceiving interface; determining a first sequence rule of the first device and a second sequence rule of a second device, wherein the first sequence rule means if the first device is required to process the command in sequence and the second sequence rule means if the second device is required to process the command in sequence; transmitting the command to the second device via the second transceiving interface; processing the command by the second device according to the second sequence rule and transmitting a response corresponding to the command to the second transceiving interface by the second device; and transmitting the response to the first device according to the first sequence rule.

Command transforming system and command transforming method

An interface connection method applied to a connection device. The connection device is configured to connect a host end having a first connection interface and a device end having a second connection interface. The interface connection method includes determining a voltage level of a detection pin; performing a first initialization when the detection pin is at a low level; providing an electrical power for detecting whether the electrical power is consumed or not when the detection pin is at a high level; sending a link signal when the electrical power is consumed; and performing a second initialization when the device end is detected to be in a ready state.

Interface connection device, system and method thereof

An error handling method for a transmission interface connecting between a first device and a second device for performing data transmission between the first device and the second device, wherein a connection type between the transmission interface and the first device is a direct interface (DI) and the connection type between the transmission interface and the second device is an indirect interface (II), and the error handling method comprises: when an error is detected at the direct interface, reporting an error event to a host of the first device; when an error is detected at the indirect interface, attempting to handle the error without letting the host discover it; and when the error detected at the indirect interface is determined as unable to be solved, reporting another error event to the host.

Error handling method and associated error handling architecture for transmission interfaces

The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

USB device and data transfer method thereof

A USB interface system capable of automatically adjusting connection speed and power consumption capability and a method thereof are provided. The method includes configuring a slave device to perform a first handshake procedure with a main device, and communicate with the main device by using a first connection specification; detecting a first power-off event by using a slave power detection module; when the first power-off event occurs, recording first power-off information by the memory unit. If the slave device is re-connected to the main device, the slave power detection module is configured to perform a second handshake process with the main device, and determine to re-communicate with the main device in a second connection specification different from the first connection specification according to the first power-off information.

USB interface system capable of automatically adjusting connection speed and power consumption capabilities and method thereof

A data-transmission-format conversion circuit has a first data transmission interface, a second data transmission interface, and a control circuit. The control circuit is coupled to the first data transmission interface and the second data transmission interface for processing data-format conversions between the first data transmission interface and the second data transmission interface. The control circuit is further used to control the second data transmission interface to switch from a first corresponding power mode to a second corresponding power mode when the first data transmission interface is switched from a first power mode to a second power mode. The control circuit is further used to control the second data transmission interface to switch from the first corresponding power mode to a third corresponding power mode when the first data transmission interface is switched from the first power mode to a third power mode.

Data-transmission-format conversion circuit and control method for data-transmission-format conversions between different high-speed data transmission interfaces

A data packet processing method comprises: receiving data packet including a key message; analyzing the key message; determining whether the data packet is a high priority data packet or a normal data packet according to a result of analyzing the first key message of the data packet; and executing an Rx high priority interrupt in response to determining that the data packet is the high priority data packet. The Rx high priority interrupt is to immediately transmit an interrupt signal to interrupt receiving of the data packets.

Data packet processing method

A liquid crystal display panel including a first substrate, a second substrate, a liquid crystal layer, a scan line, a data line intersects the scan line, an active device, a pixel electrode, an insulating layer covering the pixel electrode, an auxiliary electrode, a shielding electrode, and a first polymer stabilized alignment (PSA) layer is provided. The liquid crystal layer between the first substrate and the second substrate includes liquid crystal molecules and a monomer material. The active device includes three terminals coupled to the scan line, the data line, and the pixel electrode. The auxiliary electrode on the insulating layer is electrically connected to the pixel electrode. The shielding electrode on the insulating layer located at peripheries of the pixel electrode surrounds the auxiliary electrode. The first PSA layer between the first substrate and the liquid crystal layer is polymerized from the monomer material in the liquid crystal layer.

Liquid crystal display panel and manufacturing method thereof

A pixel unit having a display area is provided. The pixel unit includes a first substrate, a second substrate, a liquid crystal layer, and at least one ultraviolet light (UV) absorption pattern. The second substrate is disposed in parallel to the first substrate, and the liquid crystal layer is disposed between the first substrate and the second substrate. The UV absorption pattern is disposed between the first substrate and the second substrate. A part of the display area overlaps the UV absorption pattern to define at least one first alignment area, while the part of the display area which does not overlap the UV absorption pattern defines at least one second alignment area. The liquid crystal molecules of the liquid crystal layer present different pre-tilt angles in the first alignment area and the second alignment area.

Methods for manufacturing pixel unit, liquid crystal display panel, and electro-optical apparatus

A liquid crystal display (LCD) panel and a manufacturing method thereof are provided. The manufacturing method includes providing a panel including a first substrate having scan lines, data lines, an active device electrically connecting the scan and data lines, and a pixel electrode electrically connecting the active device, a second substrate having an opposite electrode, and a liquid crystal (LC) layer disposed between the first and the second substrates and having a monomer material. A first curing voltage and a second curing voltage are applied to the scan and data lines, respectively. The second curing voltage is thus transmitted to the pixel electrode. The first curing voltage is higher than an absolute value of the second curing voltage. The monomer material is polymerized to form a first polymer stabilized alignment (PSA) layer between the LC layer and the first substrate and a second PSA layer between the LC layer and the second substrate. The electrical field is then removed.

A liquid crystal display including an active device array substrate, an opposite substrate disposed above the active device array substrate and a liquid crystal layer disposed between the active device array substrate and the opposite substrate is provided. The active device array substrate has a plurality of signal lines, a plurality of active devices electrically connected with corresponding signal lines, a plurality of pixel electrodes electrically connected with corresponding active devices, and an auxiliary electrode. The auxiliary electrode is disposed between the pixel electrodes. Besides, the opposite substrate has a common electrode. The voltage difference applied between the common electrode and the pixel electrode is smaller than that applied between the auxiliary electrode and the pixel electrode. Additionally, a driving method for the above-mentioned liquid crystal display is also provided.

Liquid crystal display and driving method thereof

A pixel structure includes at least a pixel electrode, and at least an aligning electrode. The pixel electrode, which has a central opening, is disposed on a substrate. The aligning electrode, which is disposed between the pixel electrode and substrate, includes an aligning part disposed under and corresponding to the central part of the pixel electrode. The aligning voltage applied to the aligning electrode is greater than the pixel voltage applied to the pixel electrode.

Liquid crystal display panel and pixel structure thereof

Pixel unit, liquid crystal display panel, electro-optical apparatus, and methods for manufacturing the same

A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Growing community of inventors

Hsinchu, Taiwan

Sung-Kao Liu