Korea Electronics Technology Institute

Sung Ju Park

Chang Won Park

Ki Man Jeon

Young Hwan Kim

Tae Sik Kim

Jae Gi Son

Jae Hoon Song

Hyung Su Lee

Kyeong Won Yeom

Hyun Bean Yi

An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

Interconnect delay fault test controller and test apparatus using the same

Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.

Soc-based core scan chain linkage switch

A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control register controller controls a shift and update link configuration by activating the link control register. A switch switches the scan path between wrapped cores based on the link control configuration of the link control register. An output logic connects the link control register to a test data out (TDO) of the chip in case of testing on chip or cores of system on chip.

Wrapped core linking module for accessing system on chip test

Growing community of inventors

Kyunggi-do, South Korea

Sung Ju Park