Samsung Electronics Co., Ltd.

Sung-Joon Kim

Insu Choi

Wonjae Shin

Dae-Jeong Kim

Yongjun Yu

Changho Yun

Ho-young Lee

Tae-Kyeong Ko

Chanik Park

Changmin Lee

Ilho Kim

Kyung-Hee Han

Kyungjin Park

Wooseop Kim

Jinhun Jeong

Yunmi Hwang

Jinwoo Kim

Seung-Jae Lee

Min-Su Kim

Minsu Kim

Jin-Yub Lee

Jong-Hwa Kim

Dong-Yoon Kim

Kwanghee Lee

Eun-Jin Yun

Jong-Hoon Lee

Do-Han Kim

Chaeeun Lee

Mi Jin Lee

Sung-Kyu Jo

Heedong Kim

So-Ra Park

Sang-Hoan Chang

Mijin Lee

Jongyoung Lee

Jiseok Kang

Il-Su Han

Hui-Chung Byun

Hyun-Jung Yoo

Kyung Jin Park

Seung Ju Lee

Ho-Kil Lee

Min-Hyouk Kim

Kideok Han

Hyan Suk Lee

Sung Up Moon

Minsu Bae

Jongwon Jeong

Ilwoong Seo

Yukyoung Kim

Jong Young Lee

Da-Hee Jeong

Chang-Ho Yun

A memory system, a memory controller are provided. The memory system includes: a memory device; and a memory controller configured to: control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; and adaptively adjust the scrubbing cycle based on a comparison of an error count value of the memory device and a plurality of risk threshold values.

Memory controller and memory system including the same

A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.

Memory system including memory controller and memory device and method for recovering from an error thereof

Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

Electronic device managing corrected error and operating method of electronic device

A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

Memory module, memory system, and operation method of memory controller

A memory module includes; dynamic random access memories (DRAMs), a controller configured to control operation of the DRAMs, and an active device configured, in response to detection of an error occurring in at least one of the DRAMs, to generate an interrupt and store error information corresponding to the error.

Memory module and operating method

An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.

Object recognition devices, electronic devices and methods of recognizing objects

Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Memory systems having semiconductor memory modules therein that support page fault processing

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Memory system including memory module, memory module, and operating method of memory module

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Memory systems and operating methods of memory systems

A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

Memory module including a volatile memory device, memory system including the memory module and methods of operating a multi-module memory device

A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

Storage modules, methods of operating a storage module, and methods of operating a host controlling a storage module

A non-volatile memory device includes a non-volatile memory cell array, an input/output pad unit, and a peripheral circuit. The non-volatile memory device executes an operation requested by a controller. The input/output pad component provides a path through which a command and data related to the operation requested by the controller are input to the non-volatile memory device, and through which a result of execution of the requested operation is output to the controller. The peripheral circuit is configured to be loaded with a plurality of commands provided by the controller, to temporarily store program data provided by the controller to be written in the non-volatile memory cell array and data read from the non-volatile memory cell array, to adjust an execution order of the commands asynchronously with the controller based on an internal operation status of the non-volatile memory device, and to execute the commands in the adjusted execution order.

Non-volatile memory device and system capable of executing operations asynchronously, and operation execution method of the same

A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

Memory module and memory system including memory module

A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

Memory system including on-die termination and method of controlling on-die termination thereof

Growing community of inventors

Hwaseong-si, South Korea

Sung-Joon Kim