Hynix Semiconductor Inc.

Hyperconnect Inc.

Skhynix Inc.

Sung Joo Ha

Sang Il Ahn

Dong Young Kim

Ho Youb Cho

Kyung Whan Kim

Beom Su Kim

Sun Hwa Park

Martin Kersner

Ah Reum Han

Kee Yun Kim

Seung Ju Han

Seung Woo Choi

Young Soo Park

Tae Yun Kim

Seok Jun Seo

Yong Je Lee

Hyoun Taek Yong

A method of generating a reenacted image includes: extracting a landmark from each of a driver image and a target image; generating a driver feature map based on pose information and expression information of a first face shown in the driver image; generating a target feature map and a pose-normalized target feature map based on style information of a second face shown in the target image; generating a mixed feature map by using the driver feature map and the target feature map; and generating the reenacted image by using the mixed feature map and the pose-normalized target feature map.

Method and apparatus for generating reenacted image

Disclosed is a speech synthesis method including acquiring second speech data and a target text, acquiring first information includes embedding information corresponding to the second speech data, acquiring second information including embedding information of the second speech data, the embedding information in relation with components generated based on a sequence of the target text, and acquiring audio data corresponding to the target text and reflecting characteristics of speech of a speaker based on the first information and the second information.

Speech synthesis apparatus and method thereof

A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Memory, memory system, operation method of the memory, and operation of the memory system

Disclosed are a terminal, an operating method thereof, and a computer-readable recording medium. The operating method includes establishing a video call session between a first terminal and a second terminal, receiving, by the second terminal, data obtained by the first terminal, sequentially storing, by the second terminal, the data received from the first terminal in a buffer size, performing, by the second terminal, a validity check on the data stored in the buffer, and processing, by the second terminal, the data in response to a result of the validity check.

Terminal, operating method thereof, and computer-readable recording medium

A method of performing a convolutional operation in a convolutional neural network includes: obtaining input activation data quantized with a first bit from an input image; obtaining weight data quantized with a second bit representing a value of a parameter learned through the convolutional neural network; binarizing each of the input activation data and the weight data to obtain a binarization input activation vector and a binarization weight vector; performing an inner operation of the input activation data and weight data based on a binary operation with respect to the binarization input activation vector and the binarization weight vector and distance vectors having the same length as each of the first bit and the second bit, respectively; and storing a result obtained by the inner operation as output activation data.

Processor for accelerating convolutional operation in convolutional neural network and operating method thereof

A non-volatile memory device and a method for driving the same are disclosed. During a precharge operation, the bit line is precharged on the basis of a voltage applied to a common source line. The bit line is precharged or not precharged based on whether or not a selected memory cell is in an erased state or a program state.

Non-volatile memory device and method for driving the same

A semiconductor memory device includes a memory string coupled between a common source line and a bit line, a page buffer configured to supply a first precharge voltage to the bit line and to latch data corresponding to a threshold voltage level of a memory cell of the memory string, wherein the data is detected according to a shift in a voltage of the bit line, in a precharge operation, a precharge circuit configured to supply a second precharge voltage to the common source line in the precharge operation, and a voltage supply circuit configured to generate operating voltages for turning on the memory string in the precharge operation. While the first precharge voltage is supplied from the page buffer to the bit line, the second precharge voltage is supplied to the bit line through the memory string.

Semiconductor memory device and method of precharging the same with a first and second precharge voltage simultaneously applied to a bit line

Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addresses are used to intercept a mode register set command signal that enables the MRS operation at a time point at which the memory device exits from the self-refresh mode.

Method of controlling mode register set operation in memory device and circuit thereof

A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

Circuit for generating data strobe signal of semiconductor memory device

A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit. In the circuit, a local input/output line precharge operation is not performed at a continuous write mode, thereby reducing current consumption.

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Seoul, South Korea

Sung Joo Ha