Hynix Semiconductor Inc.

Sung-Joo Ha

Ho-Youb Cho

Sun-Hye Shin

Yoon-Jae Shin

Yong-Mi Kim

Sang-Hee Kang

Jae-Kwan Kwon

A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.

Circuit for transmitting and receiving data and control method thereof

An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.

Integrated circuit

A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.

Buffer circuit of semiconductor integrated apparatus

A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Differential amplifier with a feedback unit

A semiconductor device includes a transmitting unit for receiving plural bits of data to modulate the data to a 1-bit pulse signal whose pulse width corresponds to a value of the data and transferring the pulse signal to a transfer line; and a receiving unit for receiving the pulse signal transferred through the transfer line to demodulate the pulse signal to the plural bits of data.

Semiconductor device

A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.

Semiconductor memory input/output device

A semiconductor memory device includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the semiconductor memory device, when a test operation is activated.

Semiconductor memory device

An amplifying circuit of a semiconductor integrated circuit includes a data amplifier that outputs an up-signal and a down-signal amplified according to a comparison result between an up-data signal and a down-data signal in response to a control signal. The data amplifier repeats an operation of amplifying the up-signal and the down-signal according to the comparison result between the up-signal and the down-signal to be fed back to the data amplifier.

Amplifying circuit of semiconductor integrated circuit

Differential amplifier

A test signal generating apparatus for a semiconductor integrated circuit includes a fuse control unit that generates a plurality of fuse enable signals in response to a clock and a power-up signal, and a plurality of test mode fuses that individually output test mode fuse signals so as to generate test signals in response to the fuse enable signals after a test mode is completed.

Apparatus and method for generating test signals after a test mode is completed

An internal voltage generation circuit of a semiconductor device includes: a voltage detecting unit configured to detect a voltage level of an internal voltage output terminal to output a voltage detection signal; an oscillating unit configured to generate a first oscillation signal having a predefined frequency in response to the voltage detection signal; and a pumping unit configured to perform a charge pumping operation in response to the first oscillation signal and the voltage detection signal to output an internal voltage to the internal voltage output terminal, a period of the charge pumping operation being limited within an activation period of the voltage detection signal.

Internal voltage generation circuit for semiconductor device and method for generating internal voltage therein

A semiconductor memory device includes a pair of local input/output (IO) lines, a global IO line, a local driver configured to pull up/down voltage levels of the first and second local IO lines in response to input data, a global driver configured to pull up/down a voltage level of the global IO line in response to input data, and a data IO control block configured to transport output data from the local IO lines to the global driver and input data from the global IO line to the local driver.

Semiconductor memory device with bi-directional read and write data transport

A semiconductor memory device includes a data transfer line for read, a data signal transfer unit, a reset controller, and a data signal transfer unit for write. The data signal transfer unit for read receives a first data signal corresponding to a read command via the data transfer line and outputs the first data signal. The reset controller resets the data transfer line in response to a reset signal. The data signal transfer unit for write receives a second data signal corresponding to a write command, and outputs the second data signal to the data transfer line. The data transfer line is reset in response to the reset signal.

Semiconductor memory device and its driving method

A semiconductor memory device resolves skew problem due to delay difference between the case when data that is inputted through data input/output (IO) pin is transferred to one global I/O bus and the case when transferred to another global I/O bus based on data width option. The semiconductor memory device includes a first data IO pad formed at one side of a chip, a second data IO pad formed at the other one, a first global data bus receiving data from the first data IO pad, a second global data bus receiving data from the second data IO pad, a first data path for transferring data from the first data IO pad to the first global data bus, a second data path for transferring data from the first data IO pad to the second global data bus, and a third data path for transferring data inputted to the second data IO pad to the first global data bus depending on data width option, wherein data transfer time of the second data path is substantially equal to data transfer time of the third data path.

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Kyoungki-do, South Korea

Sung-Joo Ha