Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Sung Jin Jo

Ashish Khanna

Keith L Kraver

Gerhard Trauth

Divya Pratap

Bishnu Prasanna Gogoi

Yizhen Lin

Lisa Z Zhang

Marianne Maleyran

Chee Seong Chua

Raghavendra N Sridhar

An oscillator drive circuit and a trim circuit are implemented inside an integrated circuit of a sensor. The drive circuit provides an oscillating drive signal at a resonant frequency to drive a movable mass of the sensor. The drive circuit includes a phase shift circuit having an input for receiving a first signal indicative of an oscillation of the movable mass and having an output. The phase shift circuit adds a phase shift component to the first signal and produces a second signal shifted in phase by the phase shift component. The trim circuit includes a first comparator for receiving the first signal, a second comparator for receiving the second signal, and a processing element. The processing element determines a phase lag between the first and second signals and produces trim code for use by the phase shift circuit, the trim code being configured to adjust the phase shift component.

Trim circuit and method of oscillator drive circuit phase calibration

Systems and methods for converting a capacitance signal into a band-limited voltage signal for improved signal processing are disclosed herein. Such systems can include a capacitance-to-voltage converter configured to convert a capacitive signal from a capacitive device that operates at a mechanical frequency into a raw voltage signal, a clock generator configured to convert the mechanical frequency into one or more clock signals, and a filter component configured to apply a band-pass filter response to the raw voltage signal to convert the raw voltage signal into a band-limited voltage signal. The clock generator can be configured to apply the one or more clock signals to the filter component to drive a first pole and a second pole of the band-pass filter response to track the mechanical frequency of the capacitive device such that the geometric mean of the first pole and the second pole is substantially equal to the mechanical frequency.

Capacitance-to-voltage interface circuit

A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller.

System and method for evaluating a capacitive interface

An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.

Method for testing integrated circuit and integrated circuit configured to facilitate performing such a method

A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification.

Capacitance-to-voltage interface circuits

Embodiments of compact micro-electro-mechanical systems (MEMS) devices are provided, as are embodiments of methods for fabricating MEMS devices. In one embodiment, the MEMS device includes a substrate, a movable structure resiliently coupled to the substrate, and an anchored structure fixedly coupled to the substrate. The movable structure includes a first plurality of movable fingers, and a second plurality of movable fingers electrically isolated from and interspersed with the first plurality of movable fingers. The anchored structure includes fixed fingers interspersed with first and second pluralities of movable fingers in a capacitor-forming relationship. First and second interconnects are electrically coupled to the first and second pluralities of movable fingers, respectively.

Microelectromechanical systems devices and methods for the fabrication thereof

Capacitance-to-voltage interface circuit, and related operating methods

A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register.

Capacitance-to-voltage interface circuit with shared capacitor bank for offsetting and analog-to-digital conversion

The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balancing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.

Charge redistribution successive approximation analog-to-digital converter and related operating method

A MEMS sensor packaged with an integrated circuit includes switches and control circuitry. In a test mode, the control circuitry causes the switches to turn off and on such that the first and second capacitance of the MEMS sensor can be monitored individually. During a normal mode of operation, the switches are maintained such that the MEMS sensor packaged with the integrated circuit operates to produce a filtered and trimmed output reflecting the sensed phenomena.

Testing circuit and method for MEMS sensor packaged with an integrated circuit

Remote energy transmitting circuits 30, 35, 36, 37 sequentially transmit a first RF signal when activated by the controller 60. A remote unit 14 in the tire receives the first RF signal, and when the pressure in the tire is greater than a predetermined pressure, the remote unit 14 transmits a second RF signal. Via the remote receiver 20, the controller 60 determines whether the second RF signal is received within a predetermined time after transmitting the first RF signal. When the second RF signal is not received within the predetermined time, the controller 60 assumes a pressure detection failure and causes a display to indicate this condition.

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Gilbert, AZ, United States of America

Sung Jin Jo