Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Sung-jae Moon

Dong-Gyu Kim

Yoon-Jang Kim

Seong-Young Lee

Byoung-Sun Na

Eun Jeong Cho

Yun-Jung Cho

Seung-Hwan Moon

Joon-Hoo Choi

Sung-Man Kim

Sung-Hoon Yang

Nam-Soo Kang

Sahng-Ik Jun

Yong-Soon Lee

Bum-Ki Baek

Hye-Seok Na

Gwang-Bum Ko

Haeng-Won Park

Sin-Gu Kang

Yeon-Ju Kim

Kwang-Hoon Lee

Sung-Hoon Kim

Sang-Soo Kim

Jae-Hoon Lee

Hyang-Shik Kong

Seung-Soo Baek

Bong-Hyun You

Kyung-Ho Park

So-Young Kim

Kee-Bum Park

Sung-wook Kang

Tae-hyung Kim

Young-Je Cho

Su-Hyoung Kang

Eun-Guk Lee

Young-Goo Song

Back-Won Lee

Byoung-Jun Lee

Byung-Duk Yang

Sang-Yong No

Seiki Takahashi

Yeong-Beom Lee

Seon-Kyoon Mok

Seoung-Young Lee

A system on chip includes a clock generator configured to generate a clock signal, and output the clock signal to a component device external to the system on chip. The system on chip further includes a duty ratio determiner configured to determine a component duty ratio, in response to a response that is received from the component device according to the clock signal, and a duty ratio adjustor configured to adjust a current duty ratio of the clock signal to the component duty ratio, and output the clock signal of which the current duty ratio is adjusted, to the component device.

System on chip performing clock training and computing system including the same

A display device and a driving method therefor includes a plurality of unit pixels arranged in a matrix form, a plurality of gate lines extending in a row direction and connected to the unit pixels, respectively, pluralities of first and second data lines extending in a column direction and connected to the unit pixels, respectively, a plurality of charge control lines extending in the row direction and connected to the unit pixels, respectively, a plurality of gate connection lines connected to at least two adjacent gate lines, respectively, and a plurality of charge connection lines connected to at least two adjacent charge control lines, respectively.

Display device and driving method thereof

A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

Driving unit and display device having the same

A display panel is disclosed. The display panel includes a substrate, a plurality of first unit pixel and a plurality of second unit pixel. The substrate includes a first region and a second region extending in a first direction. The plurality of first unit pixels is disposed in the first region of the substrate. The first unit pixel has a first area. The plurality of second unit pixel is disposed in the second region of the substrate. The second unit pixel has a second area which is smaller than the first area.

Display panel

Gate driving unit and display device having the same

A display substrate includes a gate line, a data line, a pixel electrode, a storage line, a dual transistor, a connection transistor, a voltage-decreasing electrode, a first contact electrode and a second contact electrode. The voltage-decreasing electrode is disposed on the storage line. The voltage-decreasing electrode is connected to a connection drain electrode of the connection transistor. The first contact electrode overlaps with the first pixel part and is electrically connected to the first pixel part. The first contact electrode is connected to a first drain electrode of the dual transistor and a connection source electrode of the connection transistor. The second contact electrode overlaps with the second pixel part and is electrically connected to the second pixel part. The second contact electrode is connected to a second drain electrode of the dual transistor. Therefore, the aperture ratio of the display device may be increased.

Display substrate with dual transistor and connection transistor, method of manufacturing the display substrate and display device having the display substrate

A touchscreen display substrate includes; a plurality of pixel parts including a plurality of first pixel rows arranged in a first direction, and a plurality of pixel columns arranged in a second direction substantially perpendicular to the first direction, wherein each of the plurality of pixel parts includes a pixel electrode, and a plurality of sensing parts which sense a touch state, the sensing parts being disposed in an area corresponding to the plurality of pixel parts, and being sequentially arranged in the first direction between adjacent pixel parts of first plurality of pixel columns.

Touchscreen display substrate with a sensing part formed in an area corresponding to a plurality of pixel areas and touchscreen display apparatus having the same

A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

Photomask and thin-film transistor fabricated using the photomask

A liquid crystal display includes a lower panel and an upper panel facing each other. A liquid crystal layer is interposed between the lower panel and the upper panel. An attachment member attaches the lower panel and the upper panel and encloses the liquid crystal layer. A gate driver is integrated on the lower panel. The gate driver generates a gate signal and includes a plurality of stages. A plurality of control signal lines transmit a control signal to the gate driver. A passivation layer is disposed on the gate driver and the plurality of control signal lines. An alignment layer is disposed on the passivation layer and completely covers the gate driver and the plurality of control signal lines. The alignment layer includes a first region and a second region connected to the first region. The second region extends to an edge of the lower panel.

Liquid crystal display and manufacturing method thereof

A liquid crystal display includes a substrate, a plurality of pixel electrodes formed on the substrate, a common electrode facing the pixel electrodes, and a liquid crystal layer interposed between the pixel electrodes and the common electrode. The pixel electrode includes at least one oblique edge including a plurality of protruded and depressed portions.

A liquid crystal display includes: a gate line disposed on a substrate to transmit a first gate signal to switching elements; a data line crossing the gate line to transmit a data voltage to the switching elements; a boosting gate line disposed on the substrate to transmit a second gate signal; a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode; a first switching element connected to the first subpixel electrode; a second switching element connected to the second subpixel electrode; a boosting capacitor including a first terminal connected to the first subpixel electrode; a third switching element connected to a second terminal of the boosting capacitor; and a fourth switching element including a gate electrode connected to the boosting gate line, a source electrode connected to the second subpixel electrode, and a drain electrode connected to the second terminal.

Liquid crystal display having boosting capacitor

Disclosed are a liquid crystal display and a photomask for manufacturing the liquid crystal display. The liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including first and second sub-pixel electrodes, a first thin film transistor having first gate and source electrodes and a first drain electrode connected to the first sub-pixel electrode, a second thin film transistor having second gate and source electrodes and a second drain electrode connected to the second sub-pixel electrode, and a third thin film transistor having third gate and drain electrodes and a third source electrode connected to the second sub-pixel electrode. A first gate signal is applied to the first and second gate electrodes, a second gate signal is applied to the third gate electrode, the same data signal is applied to the first and second source electrodes, and the second drain electrode and the third source electrode are connected to each other.

Liquid crystal display and photomask for manufacturing the same

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Seoul, South Korea

Sung-jae Moon