Electronics and Telecommunications Research Institute

Sung-Jae Maeng

Jae-Jin Lee

Chang-Seok Lee

Kwang-Eui Pyun

Hyung-Moo Park

A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.

Fabrication method of gate electrode in semiconductor device

An analog/digital dual-mode power amplifier which provides a good linearity and a high efficiency comprises a first and a second power field effect transistors, and an input stage, a middle stage and an output stage. An input stage receives the input signal through an input terminal. A middle stage applies a second gate bias voltage appropriately controlled in response to an analog operating mode or a digital operating mode to a second power FET. An output stage provides matching at center frequency and has the impedance of less than 2.OMEGA. for a second harmonic and a third harmonic. Accordingly, a good linearity and high efficiency circuit can be obtained.

Growing community of inventors

Daejeon, South Korea

Sung-Jae Maeng