Samsung Electronics Co., Ltd.

Sung-Il Cho

Kyeong-Koo Chi

Nam-Gun Kim

Chang-Jin Kang

Bong-Soo Kim

Jin-Young Kim

Hyun-Chul Yoon

Cheol-Kyu Lee

Seung-Young Son

Kwan-Sik Cho

Ji-Chul Shin

In-Kyeong Yoo

Jae-Seung Hwang

Byeong-Yun Nam

Yong-Hyun Kwon

Choong-Rae Cho

Young-kyu Cho

Youn-jo Mun

Yoon-Dong Park

Makoto Yoshida

Chang-ki Hong

Jong-Kyu Kim

Chul Ho Lee

Hyun-Chul Kim

Dong-Chan Kim

Jeong-Nam Han

Jung-Min Oh

Jong-Cheol Lee

Jae-woong Hyun

Eun-hong Lee

Seung-Pil Chung

Kyoung-Sub Shin

Sang-Young Kim

Chang-Wook Moon

Hoon Sohn

Eun-ae Chung

Kun-tack Lee

Hyuk Kim

Heui-seog Kim

Doo-Young Lee

Won-Gil Han

Jun Ho Seo

Jeon Il Lee

Joon-Seok Moon

Dae-Hyuk Kang

Jin Hyuck Yu

Jae-Rok Kahng

Kyoung-Ho Jung

Seung Bo Shim

Dae-Sang Chan

Stefanovich Genrikh

Yoon-Jae Kim

Se-Jin Yoo

Byung-ho Kim

Yong-Je Lee

Ho-Tae Jin

Yong-hee Choi

Eun-Young Kang

Seok-Hyun Lim

Man-hee Han

Seung-Weon Ha

Jae Myung Choe

Jung-lae Jung

Jin-Yeol Yang

Man-Hee Han

Jae-ho Choi

Seon-ju Oh

Min-woo Song

Jun Sen

Se-gi Byun

Kyeong-Koo Ghi

Sun Taek Lim

Seung-Lo Lee

Yun-Kyu An

Byong-gook Jeong

Soon-Kyu Hwang

Jin-wook Jang

Jeong-cheol An

Dae-sang Chun

Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

Plasma treatment apparatus and method of fabricating semiconductor device using the same

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

A method of fabricating a semiconductor package includes providing a substrate on a stage, the substrate including semiconductor dies and a modified layer along a partition lane and sequentially having an adhesive film and a base film on a surface thereof so that bottom surfaces of the adhesive film and the base film face the stage and top surfaces of the adhesive film and the base film face away from the stage and the bottom surface of the adhesive film faces the top surface of the base film; separating the semiconductor dies from each other by applying a force to the substrate in a lateral direction; applying a gas pressure to a top surface of each of the semiconductor dies; and irradiating ultraviolet rays toward the adhesive film after applying the gas pressure on the top surface of each of the semiconductor dies.

Method of singulating semiconductor die and method of fabricating semiconductor package

A jig for bonding a semiconductor chip may include a pressurizing portion and at least one opening. The pressuring portion may be configured to pressurize an upper surface of the semiconductor chip bonded to a package substrate via a bump and a flux using a laser. The opening may be surrounded by the pressurizing portion. The laser irradiated to the bump and the flux may be transmitted through the opening. A vapor generated from the flux by the laser may be discharged through the opening. Thus, the contamination of the jig caused by the vapor may be prevented so that a transmissivity of the laser through the jig may be maintained.

Jig for bonding a semiconductor chip, apparatus for bonding a semiconductor chip including the jig, and method of bonding a semiconductor chip using the apparatus

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Semiconductor package and method of manufacturing the same

A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Semiconductor devices including bit line contact plug and peripheral transistor

A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Surface inspection apparatus for semiconductor chips

A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.

Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Methods of fabricating integrated circuit capacitors having u-shaped lower capacitor electrodes

Semiconductor devices including bit line contact plug and peripheral transitor

A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.

Method of fabricating semiconductor device

A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.

Method for processing a substrate using a laser beam

Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same

A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.

Method of forming semiconductor device having contact plug

Growing community of inventors

Seoul, South Korea

Sung-Il Cho