Electronics and Telecommunications Research Institute

Sung Ik Jun

Young Soo Park

Ji Man Park

Young Sae Kim

Jong Soo Jang

Sang Woo Lee

Moo Seop Kim

Yun Kyung Lee

Wan Gyun Choi

Sung Won Sohn

Kyo Il Chung

Hong Il Ju

Jin Ho On

Young Choon Woo

Baik Song An

Im Young Jung

Kyo Ii Chung

Provided is a method of dynamically controlling power in a multicore environment including a multicore processor which includes a plurality of cores and a scheduler. The method includes determining whether a management policy is set, collecting frequency change information used to change frequencies of the plurality of cores when it is determined that the management policy is set, calculating an average load of each core on a basis of the frequency change information, calculating an average frequency of each core according to the calculated average load of each core, comparing the average frequency of each core and a predetermined threshold value, and setting a next frequency of each core according to the comparison result.

Method of dynamically controlling power in multicore environment

An apparatus for hash cryptography has a hardware structure that is capable of providing both secure hash algorithm (SHA)-1 hash calculation and SHA-256 hash calculation. The apparatus for hash cryptography generates a plurality of first message data corresponding to a plurality of first rounds when the SHA-1 hash calculation is performed and generates a plurality of second message data corresponding to a plurality of second rounds when the SHA-256 hash calculation is performed by using one memory, one first register, one XOR calculator, and one OR calculator, calculates a message digest by the SHA-1 hash calculation by using the plurality of first message data when the SHA-1 hash calculation is performed, and calculates a message digest by the SHA-256 by using the plurality of second message data when the SHA-256 hash calculation is performed.

Apparatus and method for hash cryptography

A sensor signal processor apparatus having good characteristics and providing an easy and simple interface for various sensors. The sensor signal processor apparatus includes a current source, a sensor, a ramp integrator, a comparator, and a controller. The current source generates a constant current according to a preset value, and the sensor outputs a sensor voltage using the current from the current source. The ramp integrator generates and outputs an integral voltage according to an input command, and the comparator compares the sensor voltage of the sensor with the integral voltage of the ramp integrator and outputting a result of the comparison. The controller controls the generating and outputting of the integral voltage of the ramp integrator according to the comparison result of the comparator.

Sensor signal processor apparatus

There are provided a low power SHA-1 hash algorithm apparatus having a low power structure and optimized to a trusted platform module (TPM) applied to a mobile trusted computing environment and a low power keyed-hash message authentication code (HMAC) encryption apparatus using the low power SHA-1 hash algorithm apparatus, the HMAC encryption apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector; and a controller controlling operations of the key padder, data connector, and data padder, a sequence of performing a hash algorithm of the SHA-1 hash algorithm part, and storing an operation result to read data required for performing an encryption operation and store data with memory.

Low power HMAC encryption apparatus

A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors.

Current mode double-integration conversion apparatus

A garbage collection apparatus and a method using the same are disclosed. The garbage collection method comprises: making a list of objects that must be deleted from a memory; calculating a predetermined residual time for responding to an external command; deleting the listed objects from the memory during the residual time; and storing a list of remaining objects that have not been deleted from the memory during the residual time. Accordingly, communication failure due to a response delay or timeout is prevented by distributed processing loads of garbage collection.

Apparatus and method for garbage collection

A rijndael block cipher apparatus including an operational unit that efficiently performs a round operation for encrypting/decrypting a rijndael block cipher and an encryption/decryption method thereof are disclosed. The rijndael block cipher apparatus is mounted in a mobile terminal such as a cellular phone and a PDA or a smart card, which requires a high-rate and small-sized cipher processor, and can encrypt and decrypt important data that requires security at high speed and perform the round operation with respect to upper 64 bits and lower 64 bits which are divided from 128-bit input data. Thus, the cipher apparatus can reduce the time required for encryption/decryption of the rijndael block cipher and the size of the apparatus.

Rijndael block cipher apparatus and encryption/decryption method thereof

An apparatus and method for computing a SHA-1 hash function value are provided. The apparatus includes a first register unit including a plurality of registers that store a first bit string of predetermined lengths for generation of a hash function value; a second register unit storing input data in units of second bit strings with predetermined lengths, and sequentially outputting the second bit strings; a third register unit performing an operation on the first bit string of the plurality of registers and the second bit strings output from the second register unit so as to generate and store a third bit string, and updating first-bit string of the plurality of registers based on the third bit string; and an adding unit combining the first bit string stored in the first register unit, the first bit string of the third bit string stored in the third register unit, and the original initial values stored in the first register unit so as to obtain a hash function value. Accordingly, it is possible to reduce the size of the apparatus and stably compute a hash function value at a high speed.

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Daejeon, South Korea

Sung Ik Jun