Skhynix Inc.

Sung Hyun Song

Young Suk Seo

A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.

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Icheon-si, South Korea

Sung Hyun Song