Crossbar, Inc.

University of Michigan

Sung Hyun Jo

Hagop A Nazarian

Wei Lu

Tanmay Kumar

Kuk-Hwan Kim

Zhi Li

Sang Thanh Nguyen

Harry Yue Gee

Xianliang Liu

Joanna Bettinger

Mehdi Asnaashari

Steven Patrick Maxwell

Fnu Atiquzzaman

Scott Brad Herner

Lin Shih Liu

Jeremy Guy

Zeying Ren

Liang Zhao

Xu Zhao

Tianhong Yan

Mark Harold Clark

Sundar Narayanan

Natividad Vasquez

Ruchirkumar Shah

Fengchiao Joyce Lin

Xin Sun

Ping Lu

Chen-Chun Chen

Steve Maxwell

Layne Armijo

Jordan Frick

A monotonic counter implemented at least in part in non-volatile memory hardware is described herein. Compared with software counting algorithms, the disclosed embodiments significantly enhance security of disclosed monotonic counters. In some aspects of the disclosed embodiments, a non-binary coded decimal (BCD) counting algorithm can be utilized in whole or in part to enhance longevity of non-volatile memory cells storing monotonic counter values. Various aspects of the present specification disclose both a monotonic increase counter, and a monotonic decrease counter.

Monotonic counter implemented in non-volatile resistive switching memory

Improved erase techniques and apparatuses can improve performance and longevity of non-volatile memory. Various disclosed techniques include performing an erase operation(s) on a group of such memory cells, followed by a weak program operation. One or more subsequent erase-verify operations can be implemented until no erase disturb states are detected for the memory cells, or until a maximum erase-verify cycle count is reached. In one or more embodiments, additional weak program and erase-verify cycles can be implemented to enhance cycle longevity and reduce erase disturb states for the group of non-volatile memory.

Erase algorithm with a weak program pulse for non-volatile memory

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

Cryptocurrency hardware wallet on monolithic chip with common physical countermeasures and secure memory

Providing for a resistive switching memory device is described herein. By way of example, the resistive switching memory device can comprise a bottom electrode, a conductive layer, a resistive switching layer, and a top electrode. Further, two or more layers can be selected to mitigate mechanical stress on the device. In various embodiments, the resistive switching layer and conductive layer can be formed of compatible metal nitride or metal oxide materials having different nitride/oxide concentrations and different electrical resistances. Further, similar materials can mitigate mechanical stress on the resistive switching layer and a conductive filament of the resistive switching memory device.

Non-stoichiometric resistive switching memory device and fabrication methods

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification or random number generation. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Cell cycling to minimize resistive memory random number correlation

A physical unclonable function (PUF) can be implemented on a transistor of an integrated circuit device to generate PUF data. A potential difference is supplied across a gate insulator to induce a conductive breakdown in the gate insulator material. Location of the conductive breakdown within the gate insulator and in relation to the source node and drain node can be highly unpredictable, randomly resulting in a higher gate-source current or higher gate-drain current, respectively. The gate-source or gate-drain current can be measured and digitized to generate the PUF data value from the transistor. Moreover, PUF data values generated from multiple transistors can be highly non-correlated and useful for a random data sequence for cryptographic applications and other security applications.

Generating physical unclonable function data from a transistor of a semiconductor device

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Physically unclonable function (PUF) generation involving high side programming of bits

A method for erasing a memory cell includes applying a first erase to memory cells to erase the memory cells, wherein first memory cells are in a weakly erased state in response to the first erase, and wherein second memory cells are in a normally erased state in response to the first erase, thereafter applying a first weak program to the memory cells, wherein the second memory cells enter a programmed state and the third memory cells remain in the erased state in response to the first weak program, and thereafter applying a read to the memory cells to identify the second memory cells, and applying a second erase to the second memory cells to thereby erase the second memory cells.

Resistive random access memory erase techniques and apparatus

Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a nonvolatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Selector device for two-terminal memory

Physically unclonable function (PUF) generation involving programming of marginal bits

Growing community of inventors

Sunnyvale, CA, United States of America

Sung Hyun Jo