Skhynix Inc.

Sung Hyun Hwang

Jin Haeng Lee

Jae Yeop Jung

Yeong Jo Mun

Jae Hyeon Shin

Hyung Jin Choi

Se Chun Park

Dong Hun Kwak

In Gon Yang

Hyun Seob Shin

Chang Han Son

Kyu Sub Yoon

Ju Eun Lim

A memory device may include: a control circuit suitable for performing a program loop including a program operation including a program voltage application operation on a selected word line and a bit line setup operation on a plurality of bit lines and a verification operation of applying (N−1) first verification voltages to the selected word line according to a predetermined order to check N types of first program states for each of a plurality of memory cells included in the selected word line; and control logic suitable for controlling the control circuit to repeatedly perform the program loop until programming for the selected word line is completed, and controlling the control circuit to apply any one of N types of column voltages to each of the plurality of bit lines in the bit line setup operation included in a second program loop.

Memory device and operating method of the memory device

A memory device comprising: a memory cell array including memory cells coupled between a word line and a plurality of bit lines, and a control unit suitable for performing a program operation of repeating a program loop including a voltage application operation and a verification operation on the memory cells according to an Incremental Step Pulse Program (ISPP) method until the program operation is performed successfully, wherein the control unit repeatedly performs the program loop by setting a voltage level of an initial program pulse to one of first and second levels according to whether the program operation is an overwrite operation or not, wherein the initial program pulse is to be applied to the word line in the voltage application operation included in an initial program loop of the repeated program loops, and wherein the second level is lower than the first level by a first set level.

Memory device permitting overwrite program operation and operation method thereof

The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Memory device and method of operating the memory device

A memory device includes a first sub-block including word lines, a second sub-block including word lines, and a peripheral circuit configured to apply voltages to the word lines of the first sub-block and the word lines of the second sub-block. The memory device also includes control logic configured to control the peripheral circuit to perform a partial program operation of storing data in the first sub-block, when a plurality of memory cells included in the first sub-block are erased and a plurality of memory cells included in the second sub-block are programmed. The control logic includes a program operation controller for controlling the peripheral circuit to apply a verify operation to a selected word line of the word lines of the first sub-block and then apply a voltage having a constant level to the word lines of the second sub-block in the partial program operation.

Memory device and operating method for performing a partial program operation

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.

Semiconductor memory device detecting program failure, and method of operating the same

A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.

Memory device and operating method thereof

A memory device includes a cell group including a plurality of non-volatile memory cells capable of storing data and a control circuit configured to perform plural program loops for storing the data, each program loop including a program voltage application operation and a verification operation. During the respective program loop, the control circuit performs the verification operation for an N target level, an N&#x2212;1 target level lower than the N target level, and an N+1 higher than the N target level, in response to the program voltage application operation for the N target level. When a quantity of non-volatile memory cells having threshold voltages over the N+1 target level satisfies a preset criterion, the control circuit skips a next verification for a target level lower than the N+1 target level, in response to a next program voltage application operation for the N+1 target level.

Apparatus and method for programming and verifying data in a non-volatile memory device

Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

Memory device and method of operating the same

A memory device having an improved operation speed includes: a memory cell; a page buffer connected to the memory cell through a bit line; and a program operation controller for controlling an operation of the page buffer. The page buffer includes: a bit line voltage supply for providing a precharge voltage to the bit line; a sensing node voltage supply for providing a sensing node precharge voltage to a sensing node connected to the bit line; a first latch for storing first verify data; a sensing node connector for releasing connection between the bit line and the sensing node, after the first verify data is stored; and a second latch for storing second verify data determined according to the voltage of the sensing node, after the connection between the bit line and the sensing node is released.

Memory device for performing verify operation and operating method thereof

The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a program operation on a selected memory block among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform a retention acceleration operation including boosting a channel of a plurality of cell strings included in the selected memory block between a program voltage applying operation and a program verify operation during the program operation.

Semiconductor memory device and programming method thereof using a channel boosting

A memory device having an improved operation speed may include a memory block including memory cells, a peripheral circuit configured to perform a program operation of increasing each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation may include a plurality of program loops, each of the plurality of program loops may include a program voltage apply operation and a verify operation, and the control logic may control the peripheral circuit to perform verification on a highest program state during a verify operation included in a next program loop of any one program loop, when verification of a next higher program state among the plurality of program states is passed during a verify operation included in the any one program loop among the plurality of program loops.

Memory device and method of performing program operation

Provided herein may be a memory device capable of completing a foggy-fine program operation in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation on a page adjacent to a selected page among the plurality of pages, and perform a second program operation on the selected page and control logic configured to control the peripheral circuit, during the first program operation, to successively receive least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data from a memory controller, and program the LSB page data to the page adjacent to the selected page and during the second program operation, to program the LSB page data programmed to the page adjacent to the selected page, the CSB page data and the MSB page data to the selected page.

The present disclosure relates to a memory device that includes a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, which includes a plurality of program loops each including an operation of applying a program voltage to a selected word line commonly connected to the plurality of memory cells and a verify operation of applying at least one verify voltage among verify voltages respectively corresponding to target program states of the plurality of memory cells. The memory device additionally includes control logic configured to control the peripheral circuit so that the at least one verify voltage increases according to a program loop of the plurality of program loops during the program operation.

Growing community of inventors

Gyeonggi-do, South Korea

Sung Hyun Hwang