Samsung Electronics Co., Ltd.

Alogics Co., Ltd.

Sung-hyun Chung

Min-joong Rim

Jae-min Ahn

Jeong-sang Lee

Hyun-uk Shin

Provided is an interleaving method that can reduce error occurring during transmission at a receiving end in an Orthogonal Frequency Division Multiplexing (OFDM) system. According to the interleaving method, transmitted data bits are recorded in an interleaving memory; and the stored data bits are read based on a predetermined sequence to perform symbol interleaving, tone interleaving and cyclic shift simultaneously. Also, to simplify the logic of the OFDM system, the data bits transmitted from an interleaver go through Fast Fourier Transform (FFT) mapping, and the FFT mapped data bits are modulated. In short, the logic can be simplified by performing FFT mapping followed by modulation.

Interleaving method in OFDM system

An FFT apparatus for quickly processing input signals and method thereof is disclosed. In performing the FFT for processing N input signals, four N/4-point FFT units implemented by radix-2 single-path delay feedback (R2SDF) units performs the FFT with respect to the input signals, and a radix-4 computation unit performs a radix-4 computation with respect to the signals transferred from the N/4-point FFT units. Accordingly, the input signals are processed in parallel through the N/4-point FFT units, and thus a quick process of the input signals can be performed.

FFT apparatus for high data rate and method thereof

Disclosed are a method and apparatus for detecting minute oscillation in a WiBro repeater, and the WiBro repeater having the same. The method of detecting minute oscillation in a WiBro repeater includes: calculating an autocorrelation value of an input signal inputted to the repeater; calculating energy of the input signal; calculating the amount of oscillation by dividing the autocorrelation value by the energy; and comparing the amount of oscillation with a predetermined threshold value to determine whether or not the minute oscillation occurs in the repeater.

Method and apparatus for detecting minute oscillation and WiBro repeater having the same

A memory control circuit in a CD-ROM driving system is provided which controls the writing and reading of data to and from a memory in accordance with a plurality of data operations. The circuit contains a plurality of requesters, a priority level determiner, and a memory control signal generator. The requesters correspond to the plurality of data operations and respectively generate request signals. Furthermore, the requesters respectively generate physical addresses of the memory which are respectively accessed during the data operations. The priority level determiner determines the priority levels of the request signals and outputs a selection signal based on the request signals and the priority levels. Moreover, the selection signal identifies one of the data operations as a selected data operation. The memory control signal generator generates a memory control signal and a memory address which corresponds to one of the physical addresses to be accessed during the selected data operation. As a result of the above-configuration, a request to transmit data from the memory to a high-speed host computer can be quickly satisfied, and thus, the efficiency of the host computer can be maintained. Also, a method which is performed by the memory control circuit is provided.

Memory control circuit and method for a CD-ROM driving system

A method and apparatus for controlling an external memory for a CD-ROM decoder capable of smoothly performing subcode storage, read and write operations of microcomputer data, and a refresh cycle in the case where the external memory is a DRAM, without having an influence on fundamental CD-ROM decoder functions such as error correction, buffering and pickup data transmission to a host. The CD-ROM decoder includes a byte clock and master clock. The method includes outputting the byte clock upon an occurrence of six periods of the master clock, wherein the byte clock and the master clock each have first and second levels; allotting a portion of a first period of the master clock having the first level for performing a buffering operation; allotting a portion of a second period of the master clock having the first level for performing one of a refresh cycle operation, a subcode storage operation, and data read and write operations of the CD-ROM controlling microcomputer with respect to the external memory; allotting a portion having the first level of the third through sixth periods of the master clock for performing an error correction operation; allotting a portion having the second level of the first through sixth periods of the master clock for transmission to the host of the picked-up CD-ROM data, whereby the external memory is accessed.

Growing community of inventors

Seongnam-si, South Korea

Sung-hyun Chung