Samsung Electronics Co., Ltd.

Sung-Hwan Jang

Sunil Shim

Jong-Ho Moon

Hansoo Kim

Yoosang Hwang

Kyung-Tae Kim

Kiseok Lee

Youngwoo Park

Jaehoon Jang

Jae Ho Kim

Min-Woo Lee

Byoungkeun Son

Dong-Won Lee

Jae-Hoon Jeong

Woonkyung Lee

Byeong-In Choe

Jin-Soo Lim

Wonsok Lee

Sangyeon Han

Seungjae Jung

Taehyun An

Sungchul Kim

Jin-Ho Jeon

Je-Hyun Lee

Hyun-Sil Oh

Hyungeun Choi

Chul-Hwan Choi

Yong-Gab Kim

Euichul Jeong

Han-sik Yoo

Sung-Youn Chung

Jiseong Doh

Hye-Young Kwon

Jong In Yun

A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.

Semiconductor memory device

Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.

Memory device including bitline sense amplifier and operating method thereof

To reduce structure noise, input data representing an input structure is obtained and boundary conditions are set by classifying data of each of multiple structure elements of the input data as a signal component or a noise component. A smoothing operation is performed with respect to the input data and based on the boundary conditions. Output data representing an output structure is provided by reducing noise from the input structure.

Methods of and devices for reducing structure noise through self-structure analysis

A semiconductor process simulation method includes classifying a semiconductor process simulation into a plurality of blocks based on an annealing simulation, performing a shape simulation corresponding to a block selected from the plurality of blocks, and performing at least two ion implantation simulations among a plurality of ion implantation simulations corresponding to the selected block in parallel, based on result data of the shape simulation corresponding to the selected block.

Semiconductor process simulation device and simulation method thereof

A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Method of manufacturing three-dimensional semiconductor memory device in which an oxide layer is formed at bottom of vertical structure of the device

A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.

Nonvolatile memory device and method of making the same

A floating gate type nonvolatile memory device comprises a semiconductor layer, wordlines crossing over the semiconductor layer, and a memory element disposed between the wordlines and facing the semiconductor layer.

Floating gate type nonvolatile memory device and related methods of manufacture and operation

A heater assembly that is capable of uniformly heating a wafer in an apparatus for manufacturing a semiconductor device is provided. The heater assembly preferably includes a susceptor configured to support a substrate (wafer). A plurality of heaters can be disposed under the susceptor to heat the wafer. A support is preferably disposed below the heaters to support the heaters, and a power supply provides an electric current to operate the heaters. The support can include a heat-shielding portion that restricts heat conduction between the heaters. The heat-shielding portion preferably comprises heat-resistant material arranged in a groove formed on the support. The heat-shielding portion also preferably supports adjacent peripheral portions of the heaters. Electrical current provided to the heaters is preferably controlled such that the temperature of the heaters are operated in a range of about 390&#xb0; C. to 420&#xb0; C. Alternatively, a single or multiple ring-shaped heaters having an internal radiating space can be provided below a peripheral portion of the susceptor to uniformly heat the wafer.

Heater assembly for manufacturing a semiconductor device

Growing community of inventors

Bucheon-si, South Korea

Sung-Hwan Jang