Samsung Electronics Co., Ltd.

Sung-Hwan In

Hong-Beom Kim

Ho-Jin Park

Ha-Il Kim

A semiconductor memory device comprises: a write data controller for receiving predetermined bits of data inputted through data input/output pins to generate plural bits of data, and a read data controller for serially converting the plural bits of data to generate serially converted data through one of the data input/output pins during a test operation; and the write data controller for receiving plural bits of data inputted through the input/output pins to generate the plural bits of data, and the read data controller for receiving the plural bits of data to generate the plural bits of data through the data input/output pins during a regular operation, wherein the number of the plural bits is N times the number of the predetermined bits. N being a natural number.

Semiconductor memory device and test method of the same

A semiconductor chip test system and test method thereof are provided. The system having a plurality of data input/output pins, a tester for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips to be tested by the tester; a control circuit for sequentially outputting the output data from each of the plurality of semiconductor chips to the tester during a read operation and simultaneously supplying the input data from the tester to the semiconductor chips during a write operation.

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Seoul, South Korea

Sung-Hwan In