Synopsys, Inc.

Sung-Hoon Kwon

Yi-Min Jiang

Philip Hui-Yuh Tai

Philip Hui Yuh Tai

A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector 'I' and conductance matrix 'G' are used to solve for voltage drop &#x394;V, in a matrix equation G&#x394;V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.

Power network analyzer for an integrated circuit design

A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of the IC design such that an attribute (e.g. maximum voltage drop) satisfies a predetermined condition (e.g. below a user-specified limit that's scaled up by a predetermined amount). In a second stage, the computer automatically identifies a specific location in the design for having an attribute value that satisfies another predetermined condition (e.g. interior location of maximum voltage drop or peripheral location of maximum current), and automatically proposes one or more additional pads at one or more peripheral locations that are identified by a predetermined rule based on the identified specific location (e.g. having the same x-coordinate or the same y-coordinate).

Power pad synthesizer for an integrated circuit design

A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select a plan that conforms to a user-specified limit for an attribute, such as maximum voltage drop. The selected simplified plan, which identifies a total count of power wires and a width of the power wires, is used in a second stage to prepare a more detailed plan that honors the design rule checking constraints and routing blockages. The detailed plan is evaluated to check for conformance with the user-specified limit on the attribute, and if necessary the detailed plan is changed, e.g. by increasing wire width one or more times, to achieve conformance.

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Sunnyvale, CA, United States of America

Sung-Hoon Kwon