Samsung Electronics Co., Ltd.

Sung-Ho Eun

Jae-Hee Oh

Jae-Hyun Park

Hye-Jin Kim

Sungwon Kim

Ji-Hyun Jeong

Jung-In Kim

Jun-ho Choi

Jung-hoon Park

JaeHee Oh

Seul-ji Song

Na-ri Choi

Yong-tae Oh

Junghoon Park

Soon-Oh Park

Youngbae Kim

Dong-Jun Seong

Ilmok Park

Seung-Pil Ko

Seulji Song

Daehwan Kang

Heung Jin Joo

Jun-hyok Kong

Ki-deok Lee

Jeoung-gon Yoo

Jin-dong Kim

Seokjae Won

A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.

Semiconductor devices

A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.

Variable resistance memory device including symmetrical memory cell arrangements and method of forming the same

Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines.

Variable resistance memory devices and methods of forming the same

A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.

Semiconductor memory device

A variable resistance memory device including a substrate, a first insulation layer disposed on the substrate, first and second conductive lines, and memory units. The first conductive lines are arranged in a first direction on the first insulation layer and extend in a second direction. The second conductive lines are disposed over the first conductive lines, are arranged in the second direction, and extend in the first direction. The memory units are disposed in each area between the first and second conductive lines in a third direction and include a first electrode, a variable resistance pattern, a selection pattern, and a second electrode. The first electrode and the variable resistance pattern include a cross-section having an 'L' shape. The variable resistance pattern contacts an upper surface of the first electrode. The second electrode is disposed on the variable resistance pattern. The selection pattern is disposed on the second electrode.

Variable resistance memory device and a method of manufacturing the same

A semiconductor device includes first conductive lines and first and second insulation patterns on a substrate, first structures spaced apart from each other on the first conductive lines, a variable resistance pattern on the first structures, and a second electrode on the variable resistance pattern. The first conductive lines extend in a first direction. The first structures include a switching pattern and a first electrode sequentially stacked. The first insulation pattern fills a space between the first structures in a second direction and the first insulation pattern has a first top surface higher than a top surface of the first structures. The second insulation pattern fills a space between the first structures in the first direction, and the second insulation pattern has a second top surface higher than a top surface of the first structures. The variable resistance pattern fills an opening defined by the first and second insulation patterns.

Semiconductor devices and methods of manufacturing the same

A method for controlling a server connected to a photographing apparatus is provided. The control method includes receiving status information of the photographing apparatus from the photographing apparatus, searching a schedule for using the photographing apparatus from pre-stored scheduling information, determining whether the searched schedule and the status information of the photographing apparatus satisfy preset conditions, respectively, and transmitting notification information to a user terminal apparatus when the conditions are satisfied.

Server for photographing apparatus and method of providing status notification of photographing apparatus

A digital photographing apparatus and a method of controlling the same. A method of controlling a digital photographing apparatus, the method including determining whether a condition for changing an environment setup of the digital photographing apparatus is satisfied; if the condition is satisfied, searching for an environment setup to be changed according to the condition; and changing the environment setup according to the condition.

Digital photographing apparatus and method of controlling the same

Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions.

Semiconductor memory devices having strapping contacts

A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.

Variable resistance memory devices having reduced reset current

A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern.

Methods of manufacturing phase change memory devices

A method of controlling a digital photographing apparatus including a plurality of display units includes displaying a replay image file on a first display unit, determining whether additional information exists in the replay image file, searching for the additional information when the additional information exists in the replay image file, and displaying the additional information on a second display unit.

Digital photographing apparatus, method of controlling the same, and computer-readable storage medium

An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.

Memory devices including decoders having different transistor channel dimensions and related devices

A digital photographing apparatus and a method of controlling the digital photographing apparatus prevent a touch malfunction from occurring while holding the digital photographing apparatus by having a touch protection area in the digital photographing apparatus. The digital photographing apparatus includes a large-sized touch screen on one surface thereof, wherein the touch screen includes: a touch area which inputs a touch from a user and executes icons corresponding to the touch; and a touch protection area which is not activated by the touch when the touch from the user is input on the touch screen.

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Seoul, South Korea

Sung-Ho Eun