Samsung Electronics Co., Ltd.

Sung-ho Choi

Kyungho Lee

Youngchan Kim

Younggu Jin

Jung Bin Yun

Tae-seong Jang

Disclosed is a complementary metal oxide semiconductor (CMOS) image sensor. The image sensor comprises a first separation zone in a substrate, the first separation zone defining first and second pixel regions arranged in a first direction, the first separation zone including first parts substantially parallel extending in the first direction, and the substrate including a first active region vertically overlapping one of the first parts and a second active region vertically overlapping another of the first parts. The image sensor further comprises first and second photoelectric conversion devices arranged in the first direction on at least one of the first and second pixel regions in the substrate, and a source follower gate on the first active region of the substrate.

CMOS image sensors

Provided is a depth sensor which includes a pixel and a row driver that controls the pixel, the pixel including a first tap, a second tap, a third tap, and a fourth tap, an overflow transistor, and a photoelectric conversion device. Each of the first tap, the second tap, the third tap, and the fourth tap includes a photo transistor, a transfer transistor, and a readout circuit. In a first integration period of a global mode, the row driver activates a second photo gate signal controlling the photo transistor of the second tap and a third photo gate signal controlling the photo transistor of the third tap. In a second integration period of the global mode, the row driver activates a first photo gate signal controlling the photo transistor of the first tap and a fourth photo gate signal controlling the photo transistor of the fourth tap.

Depth sensor and method of operating the same

A semiconductor memory device having a bitline coupling scheme capable of preventing sensing speed from lowering due to variations in an external power supply is provided. The semiconductor memory device includes a memory cell array which includes a plurality of memory cells, a bitline and a complementary bitline which are connected to the memory cell array, a coupling capacitor one end of which is connected to either the bitline or the complementary bitline and the other end of which a control signal is applied to, a bitline sensing amplifier which senses and amplifies a difference in the voltage between the bitline and the complementary bitline, and a control circuit which generate the control signal. Here, an internal power supply generated by dropping an external power supply applied from the outside of the semiconductor memory device is used as a power supply of the control circuit.

Semiconductor memory device having bitline coupling scheme capable of preventing deterioration of sensing speed

A semiconductor memory device including a plurality of normal cell blocks including a plurality of normal memory cells for storing data, a plurality of redundancy cell blocks, a plurality of redundancy memory cells for substituting for defective normal memory cells, and at least one ECC cell block including a plurality of ECC memory cells, for substituting for defective normal memory cells in response to a mode signal.

Growing community of inventors

Suwon, South Korea

Sung-ho Choi