Samsung Electronics Co., Ltd.

Sung-Hae Lee

Jin-Gyun Kim

Ki-Hyun Hwang

Young-sun Kim

Eun-Young Lee

Young-Seok Kim

Jae-young Ahn

Ji-Hoon Choi

Jung-Ho Kim

Myoung-Bum Lee

Ki-yeon Park

Jung-Geun Jee

Hong-suk Kim

Suk-Jin Chung

Yong-Woo Hyung

Man-Sug Kang

Jun-Noh Lee

Hee-Seok Kim

Dong-Kyum Kim

Sang-Ryol Yang

Ju-Wan Lim

Koong-Hyun Nam

Min-kyung Ryu

Byong-Sun Ju

Eun-Yeoung Choi

Hyun-Yong Go

Jin-Tae No

In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Methods of manufacturing semiconductor devices including an oxide layer

A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.

Vertical memory devices including indium and/or gallium channel doping

Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

Nonvolatile memory devices and methods of manufacturing the same

A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Nonvolatile memory device and method of fabricating the same

A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

Method for forming a low-k dielectric layer for a semiconductor device

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Suwon-si, South Korea

Sung-Hae Lee