Samsung Electronics Co., Ltd.

Sung-Gil Choi

Jong-Kyu Kim

Sang-sup Jeong

Kuk-Han Yoon

Jin-Young Kim

Tae-hyuk Ahn

Bum-Soo Kim

Jong-chul Park

Won Jun Lee

Yong-Joon Choi

Doo-Young Lee

Heung-sik Park

Hyun-chul Yoon

Ki-jin Park

Sang-Dong Kwon

Sang Sup Jeong

Jang-Bin Yim

Dae Hyuk Chung

Tae Hyuk Ahn

A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

Semiconductor devices

Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation

In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

Contact structure and method of forming the same

Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

Semiconductor devices having fuses and methods of forming the same

A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH F gas; and etching the oxide layer while stopping the supply of CH F gas to the etching process.

Method for preparing semiconductor including formation of contact hole using difluoromethane gas

A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.

Method of manufacturing a cylindrical storage node in a semiconductor device

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Yongin-si, South Korea

Sung-Gil Choi