Samsung Electronics Co., Ltd.

Iljin Co., Ltd.

Sung-Geun Lee

Jung-Bae Lee

Hyun-Woo Kim

Hyuk Sang Kwon

Se Woong Jeong

Min Kook Park

Soon Chan Kwon

Young In Yoon

Byong Suk Yu

Tae-Sung Kwon

Ig-Jin Kwon

Jing-Man Han

A hybrid arm according to an embodiment of the present disclosure may include: a first body made of a metal material and formed with a plurality of end portions; a second body formed so as to fill an inner side of the first body by being insert-injection-molded to the first body; and a ball joint formed integrally at a first end portion among the plurality of end portions of the first body. The ball joint may include: a reinforcement member coupled to the first end portion; a bearing member formed with a space therein; a ball stud including a ball rotatably inserted into the space of the bearing member and a rod extending upward of the ball; and a housing interposed between the reinforcement member and the bearing member and formed integrally with the second body.

Hybrid arm and method of manufacturing same

A Bluetooth pairing method in an electronic device is provided. The method includes detecting a change of a switching state of a switch of the electronic device, selecting a Bluetooth Device (BD) address according to the changed switching state among a plurality of stored BD addresses, and applying the selected BD address to a Bluetooth pairing. The method can facilitate Bluetooth pairing to selectable types of host devices.

Electronic device and operating method using bluetooth

A digital delay locked loop for a synchronous semiconductor memory device reduces power consumption by disabling the stages of the delay locked loop that are not required for generating an internal clock signal that is synchronized with an external system clock signal. The delay locked loop includes a first synchronous delay line formed from a plurality of serially connected unit delayers, a second synchronous delay line formed from a second plurality of serially connected unit delayers, a plurality of phase detectors arranged in successive order to compare the external clock signal to the plurality of delayed clock signals and generate a plurality of enable signals, and a plurality of switches arranged in successive order to select a delayed clock signal from the second delay line as an internal clock signal. Each stage includes one of the unit delayers in the first delay line, one of the unit delayers in the second delay line, one of the phase detectors, and one of the switches. Each of the phase detectors generates a carry signal if the clock signal from its stage is synchronized with the system clock or if it is downstream from the stage that is synchronized. The carry signal from each stage is coupled to the next successive stage. Each of the stages has one or more operation cutting circuits to disable the stage responsive to an active carry signal from the previous stage. The operation cutting circuits can be included in the phase detectors and the unit delayers in each stage to disable inverters in the unit delayers and latches in the phase detectors to conserve power in stages that are not necessary for generating the internal clock signal.

Digital delay locked loop for reducing power consumption of synchronous semiconductor memory device

An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Internal clock generator

Growing community of inventors

Seoul, South Korea

Sung-Geun Lee