Taiwan Semiconductor Manufacturing Comp. Ltd.

Sung-Feng Yeh

Ming-Fa Chen

Hsien-Wei Chen

Chen-Hua Douglas Yu

Tzuan-Horng Liu

Chao-Wen Shih

Jie Chen

Nien-Fang Wu

Ching-Pin Yuan

Chih-Chia Hu

Jian-Wei Hong

Wen-Chih Chiou

Ying-Ju Chen

Sen-Bor Jan

Min-Chien Hsiao

Hui-Wen Liu

Wen-Ching Tsai

Chuan-An Cheng

Chi-Hwang Tai

Ching-Jung Yang

Kuo-Chiang Ting

Ta Hao Sung

Chung-Shi Liu

Ming-Da Cheng

Der-Chyang Yeh

Hsiu-Jen Lin

Meng-Tse Chen

Hui-Min Huang

Cheng-Feng Chen

Ta-Hao Sung

Gao-Long Wu

Ming-Zhi Yang

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

Package

An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad being in the warpage control dielectric layer, the bond via being electrically coupled to the redistribution pad.

Semiconductor device and method

A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

Methods of fabricating package structure

An integrated circuit includes a conductive pad. In some embodiments, the conductive pad includes at least one dielectric pattern therein, wherein the at least one dielectric pattern penetrates a surface of the conductive pad. In some embodiments, the conductive pad includes a conductive main body and at least one hole in the conductive main body, wherein the at least one hole penetrates a surface of the conductive main body.

Integrated circuits

A method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.

Integrated circuit package and method of forming the same

A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.

3DIC with heat dissipation structure and warpage control

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

Package structure

A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

Package-on-package device

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Integrated circuit packages and methods of forming the same

A semiconductor package includes a first die and a through via. The through via is electrically connected to the first die. The through via includes a first conductive layer having a first width, a second conductive layer having a second width different from the first width and a first seed layer disposed aside an interface between the first conductive layer and the second conductive layer.

Semiconductor packages

A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.

A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.

Package and manufacturing method thereof

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

Stacking structure, package structure and method of fabricating the same

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

Die stack structure and manufacturing method thereof

In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

Growing community of inventors

Taipei, Taiwan

Sung-Feng Yeh