Hanwha Chemical Corporation

Hynix Semiconductor Inc.

Sung Eun Park

Jong Goo Jung

Hyung Hwan Kim

Ok Min Moon

Kwang Kee Chae

Young Bang Lee

Hee Dong Lee

Dong-ho Lee

Jiwoong Kim

Gui Ryong Ahn

Hyo Jin Jeon

Jea Sung Park

Ji Ho Kim

Kyu Hak Park

Hyun-Cheol Ryu

Eun-Jeong Kim

A polysilicon manufacturing apparatus according to an exemplary embodiment of the present invention includes: a reactor in which a reactive gas is introduced to perform a polysilicon manufacturing process by a chemical vapor deposition (CVD) method; and a slit-type nozzle installed at the reactor and spraying a gas inside the reactor to prevent absorption of silicon particles during a process.

Polysilicon manufacturing apparatus

Provided is a polysilicon manufacturing apparatus including a reactor disposed on a base plate to form a reaction chamber, a pair of electrical feedthroughs installed on the base plate to be extended to the inside of the reaction chamber, rod filaments installed on the electrical feedthroughs in the reaction chamber and connected to each other by a rod bridge at the upper end to form a silicon rod by chemical vapor deposition of source gas introduced to a gas inlet, and a cooling jacket inserted to a through-hole provided at the upper side of the reactor to be supported to the base plate, connected to a gas outlet formed on the base plate by forming a gas passage discharging the gas after reaction, and introducing and circulating a low-temperature coolant to a coolant passage from the outside of the reactor by forming the coolant passage at the outside of the gas passage to discharge a high-temperature coolant to the outside of the reactor.

The present invention relates to a method for manufacturing polysilicon. According to the present invention, meltdown can be prevented during the growth of silicon rod, and a polycrystalline silicon rod having a larger diameter can be shortly manufactured with a minimal consumption of energy.

Method for manufacturing polysilicon

An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

Isolation layer having a bilayer structure for a semiconductor device and method for forming the same

A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is not filled; forming a third insulation dielectric layer over the second insulation dielectric layer so that the second recess pattern is filled; and removing the third, second, and first insulation dielectric layers formed over the active region including the first recess pattern and the isolation structure between the second recess patterns.

Method for manufacturing a semiconductor device capable of preventing the generation of a bridge between a recess gate and a PLC plug

Growing community of inventors

Seoul, South Korea

Sung Eun Park