Skhynix Inc.

Sung Eun Lee

Jung Hyun Kwon

Jae Sun Lee

Jingzhe Xu

Du Hyun Kim

Jae Il Lim

Young Ook Song

Bo Ra Kim

A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

Redundancy analysis circuit and memory system including the same

A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.

Parity generation circuits for a plurality of error correction levels, memory controllers, and memory modules including the parity generation circuits

A memory system may be provided. The memory system may include a memory apparatus including a plurality of memory cells. The memory system may include and a controller configured to control a write operation and a read operation with respect to the memory apparatus, detect an error occurrence position by performing the write operation and the read operation on a corresponding region of the memory apparatus in which an error occurs based on error occurrence address information generated in the read operation while changing a level of data to be written, and determine a type of error based on the detected error occurrence position.

Nonvolatile memory system and error determination method thereof

A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

Growing community of inventors

Icheon-si, South Korea

Sung Eun Lee