Skhynix Inc.

Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Sung-Eun Lee

Jung-Hyun Kwon

Sang-Gu Jo

Kwang-Young Choi

Yong-Ju Kim

Do-Hyun Kwon

Jung-Kyu Lee

Min-Jung Lee

Il-Jeong Lee

Jing-Zhe Xu

Kyung-Hoon Kim

Joo-Sun Yoon

Jae-Hyun Ahn

Kyou-Woong Kim

Ki-Wan Ahn

Jae-Sun Lee

Han-Kyu Chi

Myeong-Jae Park

Yong-Jae Jang

Dong-Rak Shin

Jin-Taek Kim

Joon-Yung Park

Woo-Yeol Shin

Young-Hoon Cheong

Sang-Il Park

Jong-Hyun Park

Kyoung-Hoon Kim

Kyu-Young Kim

Je-Kook Kim

Young-Jin Park

Moo-Soon Ko

Seung-Gyu Jeong

Yu-Dong Bae

Kyung-Won Park

Jeong-Hun Seo

Sung-Ha Park

Hyun-Jung Mun

Jung-Oh Sung

Kyoung-Won Kim

Wooin Choi

Ja-Hyun Koo

Kang-Jun Ko

Jongik Won

Min-Gi Kim

Hyun-Jung Moon

Insun Choi

Jong-Ik Won

In-Geol Lee

Various embodiments of the present invention relate to an electronic device and a charging control method therefor. The electronic device may comprise: a connection terminal for performing wired communication with an external electronic device; and at least one processor functionally connected to the connection terminal, wherein the at least one processor detects connection of a charging device through the connection terminal, receives state information of at least one adjacent terminal located next to a power terminal of the connection terminal, and controls charging power to be supplied thereto through the charging device, on the basis of the received state information of the adjacent terminal. In addition, various other embodiments are possible.

Electronic device and charging control method therefor

A display substrate includes a data line extending in a first direction, a first transistor including a first channel area overlapping the data line and a first control electrode which overlaps the first channel area and has a substantially same shape as that of the first channel area in an overlap area in which the first control electrode overlaps the first channel area, a scan line extending in a second direction crossing the first direction, a first voltage line extending in the first direction and transfers a first driving signal, a first capacitor including an extension electrode which overlaps the first control electrode and extends in the second direction from the first voltage line and a second capacitor including an overlap electrode overlapping the data line.

Display substrate and display apparatus including the same

An electronic device and a method for sensing moisture in an electronic device are provided. The method for sensing moisture in an electronic device includes sensing moisture introduced into a connector of the electronic device in a state where one or more functions executable by connection of the connector with an external electronic device are activated. Further, the method includes deactivating the one or more functions based on the sensing; determining whether the introduced moisture is removed in a state where the one or more functions are deactivated; and activating the one or more functions if the moisture is removed.

Electronic device and method for sensing moisture in an electronic device

A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.

Memory device, memory system, and operation method thereof

A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

Memory device, operating method thereof, and operating method of memory system including the same

A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

Memory system and operation method thereof

A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Memory system for controlling read voltage using cached data and operation method of the same

An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.

Memory controller, memory system including the same and operation method of memory controller

An error correcting method of a memory system includes: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fail chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.

Memory module, memory system including the same, and error correcting method thereof

A memory device may include a memory cell array having a plurality of memory cells, and a controller suitable for reading data of a memory cell corresponding to an address of write data, among the memory cells, and comparing the write data and the read data to check specific bits different from corresponding bits of the read data, among a plurality of bits of the write data, according to a write operation request. The controller may output a check result to outside after a preset time from the write operation request.

Nonvolatile memory device and operating method thereof

An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.

Memory system and error correcting method of the same

The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.

Memory systems and operation method thereof

A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. The detector may generate an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.

Memory controller, memory system including the same and operating method thereof

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Gyeonggi-do, South Korea

Sung-Eun Lee