Sandisk Technologies Inc.

Sung-En Wang

Jonathan Huynh

Jongmin Park

Feng Q Pan

Khin Htoo

Steve Choi

Supraja Sundaresan

Man Lung Mui

Seungpil Lee

Hao Nguyen

Tien-Chien Kuo

Bo Lei

Sagar Magia

Trung Pham

Juan Lee

Masahide Matsumoto

Shankar Guhados

Albert Chang

Primit Modi

Matt Chen

Jiang Yin

Disclosed is a device including a distributed controller and a common controller. The distributed controller includes a first circuit to generate an output voltage according to a control signal. The common controller includes a common feedback loop coupled to the distributed controller. The common feedback loop includes an amplifier circuit to generate the control signal, and a second circuit coupled to the amplifier circuit. The second circuit replicates the first circuit and stabilizes the control signal.

Memory control circuit with distributed architecture

Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.

Bias control circuit with distributed architecture for memory cells

Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. Rather than diving the load directly, a fixed pump output voltage is used to supply a step-down regulator, which it turn drives the load at the selected voltage. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory.

Charge pump based over-sampling with uniform step size for current detection

Techniques and apparatuses for identifying weak charge pumps and for setting an optimal clock period for charge pumps to minimize variations in a current-voltage characteristic. A current sink which absorbs a specified current is connected to an output node of a charge pump. In one approach, a success or fail status is set for a charge pump by driving it with a specified clock period in a constantly pumping mode and determining if the output voltage reaches a specified output voltage. In another approach, a success or fail status is set for a charge pump by driving it with a specified clock period in a regulation mode and determining if the period in which the output voltage cycles is a specified multiple, e.g., 2&#xd7;, of a period of the clock signal. In another approach, an optimal clock period is determined.

Charge pump strength calibration and screening in circuit design

A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.

Multi-clock generation through phase locked loop (PLL) reference

In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time constant associated with charging the far end of such lines from the near end, at which the circuitry is connected. While driving a discharged line from the near end, the number of clock cycles for the current to drop from a first level to a second level can be used to estimate the time constant for the far end. Alternately, the line can be initially charged up, after which the current is monitored at the near end. The differences in time constants for different word lines can be used to vary the time used when accessing a selected word line.

Single ended word line and bit line time constant measurement

To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.

Self-adjusting regulation current for memory array source line

To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation.

Dynamic regulation of memory array source line

An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.

LDO/HDO architecture using supplementary current source to improve effective system bandwidth

Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.

Amplitude modulation for pass gate to improve charge pump efficiency

A pre-charging circuit, such as can be used to pre-charge a data bus, is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connected to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.

Pre-charge circuit with reduced process dependence

In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition

In a nonvolatile memory array that stores randomized data, the program level&#x2014;the number of states per cell stored in a population of memory cells&#x2014;is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.

Common line current for program level determination in flash memory

Techniques are presented for improving the wake-up response of voltage regulation circuits. A first set of techniques relate to the inputs an op-amp in a regulation circuit. In regulated operation, one input receives feedback from the regulator's output. Instead, during reset, after resetting the op-amp's output node to the supply level, this input of op-amp is instead connected to ground in order to increase the amount of tail current through the op-amp in order to more quickly bring down the op-amp's output node. A detection circuit is introduced to determine when the op-amp's input is reconnected to receive feedback. In a complementary sets of techniques, when the circuit on which the regulator is formed receives an enable signal and the output of the regulator will be needed for an operation, and when the regulator is not yet back at operating levels, its supply is temporarily shorted to the supply level.

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San Jose, CA, United States of America

Sung-En Wang