Hannstar Display Corporation

Hannstar Display (nanjing) Corporation

Sung-Chun Lin

Hsuan-Chen Liu

Chien-Ting Chan

Chia-Hua Yu

Yi-Chung Juan

Tean-Sen Jen

Hsien-Tang Hu

Chang-Ching Yeh

Hsu-Ho Wu

Kuo-Sheng Lee

Chen-Yin Su

Kun-Chen Lee

Chen-Hao Su

Wei-Chih Hsu

Chung-Lin Chang

Chia Hua Yu

Chia-Te Liao

Te-Cheng Chung

Ding-Wei Liu

Yu-Tuan Hsu

Wen-Chi Lin

Wei-Chi Lin

Sweehan Jui-Hsien Yang

Po-Yi Chen

Kun Cheng Lee

Meng-Ju Li

Huang-Chen Kao

Yi-Tse Lin

A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Notched display panel

A gate driving circuit is provided, which includes shift registers and a reset signal line. The shift registers respectively provide scan signals to gate lines of a display panel. Each shift register includes a precharge unit and pull-up unit. The precharge unit is coupled to a first node and outputs a precharge signal through the first node. The pull-up unit is coupled to the first node and the second node and outputs one of the scan signals to a corresponding one of the gate lines through the second node. The reset signal line is coupled to the shift registers and provides a reset signal to the shift registers. The reset signal is used to reset the shift registers after the shift registers respectively output the scan signals. The reset signal line is arranged between a layout area of the precharge unit and a layout area of the pull-up unit.

Gate driving circuit and display panel

A reflective LCD panel includes a color filter substrate, an array substrate, a liquid crystal layer and a polarizing film. The array substrate and the color filter substrate are disposed oppositely. The liquid crystal layer is disposed between the color filter substrate and the array substrate and has an alignment direction. The polarizing film is disposed on the color filter substrate, and color coordinates of the polarizing film in the CIE1976 color space are (a, b), wherein 0.05&#x2264;a&#x2264;0.2 and &#x2212;5&#x2264;b&#x2264;0. The liquid crystal layer has a birefringence difference &#x394;n, the liquid crystal layer has a thickness (d), when the reflective LCD panel is in a white frame, 2&#x394;n*d=&#x394;&#x3bb; is satisfied, &#x394;&#x3bb; is the optical path difference obtained when a forward light vertically enters the liquid crystal layer and is reflected by the array substrate, and 120 nm&#x2264;&#x394;n*d&#x2264;170 nm.

Reflective LCD panel

The present invention provides a display panel including a non-rectangular display area. The display panel includes a first pixel row. The first pixel row includes a plurality of inner pixels and a plurality of end pixels. The inner pixels are disposed in the non-rectangular display area, and the end pixels are disposed between an end of the first pixel row and the inner pixels. An area of a display region of each of the end pixels is less than an area of a display region of each of the inner pixels. In the first pixel row, areas of a plurality of display regions of the end pixels are increased along a direction from the end of the first pixel row toward the inner pixels.

Display panel

A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Display panel having a test line therein

A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers. The shift registers are configured to respectively provide scan signals to gate lines of a display panel. One of the shift registers includes a pre-charge unit, a pull-up unit and a reset unit. The pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node. The pull-up unit is coupled to the first node and a second node and is configured to output one of the scan signals to the second node. The reset unit is coupled to the first node and the second node and is configured to receive a reset signal. A voltage level of the reset signal switches after the gate driving circuit scans the gate lines sequentially in a frame period.

A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Thin film transistor substrate and display device

A liquid crystal display device includes a plurality of pixel units, an electrode line surrounding the pixel units, at least one gate driver coupled with the pixel units via a plurality of gate lines, and at least one electrostatic discharge protection circuit coupled with the at least one gate driver and the electrode line.

Liquid crystal display

The present invention provides a driving circuit and a display device. The driving circuit is disposed on a substrate of the display device. The driving circuit includes thin film transistors (TFTs), a capacitor and clock signal lines. Each of the TFTs includes a gate, a source and a drain. The capacitor is coupled to at least one of the TFTs, and includes a first and a second electrode. The material of the first and the second electrode includes a transparent conductive material. The clock signal lines extend along a first direction. The source and the drain of at least two of the TFTs respectively extend along a second direction. The angle between the first direction and the second direction is between 80 degrees and 100 degrees. At least a partial structure of the capacitor is located in a gap between adjacent ones of the TFTs.

Driving circuit and display device with enhanced moisture prevention capability

The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1to Nstage shift registers for respectively generating and sequentially outputting 1to Nstage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1and 2stage shift registers to generate the 1and 2stage scan signals respectively, and the starting signal is utilized to reset the 3to Nstage shift registers.

Gate driving circuit and display apparatus

The present invention relates to a display panel and a gate driving circuit of the display panel. The gate driving circuit is disposed on a first substrate and includes a first transistor unit. The first transistor unit is disposed on the first substrate and includes a first gate block, a second gate block, and a first connection portion. The first connection portion is electrically connected to the first gate block and the second gate block. At least a gap is formed between the first gate block and the second gate block. The display panel includes the first substrate, the gate driving circuit, a second substrate, and a sealant. The second substrate is disposed corresponding to the first substrate. The sealant is formed between the first substrate and the second substrate.

Display panel and gate driving circuit thereof

A shift register circuit is disclosed. The shift register circuit includes a first gate driving module, a second gate driving module, a first discharging module, and a second discharging module. The first gate driving module has a first node and a first output terminal. The second gate driving module has a second node and a second output terminal. The first discharging module is coupled to the first node, the second node, and the first output terminal respectively. The second discharging module is coupled to the second node, the first node, and the second output terminal respectively. Both the first discharging module and the second discharging module include ten transistors respectively.

Shift register circuit with two discharging modules

A shift register includes a primary circuit and a secondary circuit including an inverting circuit and a pull-down circuit. The pull-down circuit includes a first transistor. The primary circuit has an output terminal, a first and a second input terminals, and is electrically connected to a first common terminal. The secondary circuit is electrically connected to the first common terminal. The pull-down circuit is electrically connected to the inverting circuit. The first transistor has a first top gate, a first bottom gate, a first first electrode and a first second electrode, wherein the first second electrode is configured to receive a first voltage level, the first top gate is configured to receive a second voltage level, and the second voltage level is higher than the first voltage level.

Shift register and display device

A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.

The invention discloses a gate driving circuit and a display device. The gate driving circuit includes first to eighth dock signal lines and first to Nstage first shift registers, where N is an integer greater than or equal to 9. The first to eighth clock signal lines are configured to provide first to eighth clock signals, respectively. The istage first shift register is coupled to one of the first to eighth clock signal lines and receives one of the first to eighth clock signals, a first input signal and a second input signal and outputs an istage first output signal, where i is any integer from 1 to N.

Growing community of inventors

Tainan, Taiwan

Sung-Chun Lin