Skhynix Inc.

Sung Chun Jang

Kyung Whan Kim

Min Sik Han

Jin Il Chung

Hak Song Kim

A semiconductor device includes an internal command generation circuit configured to generate a synthesized command from a command which is inputted in synchronization with any one of a first internal clock and a third internal clock generated by dividing a frequency of a clock, and configured to generate a first internal command and a second internal command by delaying the synthesized command depending on a detected input time of the command. The semiconductor device also includes a data transmission circuit configured to generate transmission data from data in synchronization with any one of the first internal command and the second internal command.

Semiconductor device

A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Semiconductor device performing duty ratio adjustment operation

A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Growing community of inventors

Icheon-si, South Korea

Sung Chun Jang