Spansion Llc.

Sung-Chul Lee

Zhizheng Liu

Darlene G Hamilton

Yi He

Sung-Yong Chung

Ming Sang Kwan

Nancy S Leong

Guowei Wang

Xuguang Alan Wang

Yugi Mizuguchi

Mark W Randolph

Kuo-Tung Chang

Gulzar Ahmed Kathawala

Sheung-Hee Park

Yu Nan Sun

Richard M Fastow

Wei Zheng

Meng Ding

Amol Ramesh Joshi

Edward Franklin Runnion

Ming-Sang Kwan

Kazuhiro Mizutani

Sean Michael O'Mullan

Gwyn Robert Jones

John Anthony Darilek

Adam Shackleton

Qiang Lu

Yuji Mizuguchi

Yanxia (Emma) Lin

Xianmin Yi

Yanxiang Liu

Jacob Marcantel

Rick Anundson

Xiaojian Chu

Abhijit Raghunathan

Asif Arfi

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb

Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.

Room temperature drift suppression via soft program after erase

A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.

Flash memory device having increased over-erase correction efficiency and robustness against device variations

A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

Negative wordline bias for reduction of leakage current during flash memory operation

A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the cell by applying a positive stress to the word line after a program-erase cycle.

Positive gate stress during erase to improve retention in multi-level, non-volatile flash memory

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Cupertino, CA, United States of America

Sung-Chul Lee