Skhynix Inc.

Hynix Semiconductor Inc.

Sung Cheoul Kim

Kang Sik Choi

Nam Kyun Park

Hyun Jeong Lee

Soo Gil Kim

Myoung Sub Kim

Joon Seop Sim

Gap Sok Do

Hae Chan Park

Suk Ki Kim

Jang Uk Lee

Tae Ho Kim

A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.

Data processing system having combined memory block and stack package

A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.

Combined memory block and data processing system having the same

A memory cell array includes a semiconductor substrate, a first word line formed on the semiconductor substrate, a second word line formed on the semiconductor substrate and extending substantially parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, first active pillars formed within the first word line and arranged along the first word line at a first interval, and second active pillars formed within the second word lines, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween.

Memory cell array and variable resistive memory device including the same

A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.

Semiconductor integrated circuit device, method of manufacturing the same, and method of driving the same

A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

High-integration semiconductor memory device and method of manufacturing the same

Semiconductor intergrated circuit device, method of manufacturing the same, and method of driving the same

A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line.

Growing community of inventors

Gyeonggi-do, South Korea

Sung Cheoul Kim