Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Tsinghua University

Sung Cheol Shin

Yoo Hwan Kim

Soo Woong Lee

Yo Sub Moon

Ki Sung Kwon

Jin Taek Lee

Woogeun Rhee

Zhihua Wang

Gyu Suck Kim

Xueyi Yu

Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (&#x3a3;&#x394;) modulator to operate at a low frequency without generating false lock and glitch noise.

Delay locked loop using hybrid FIR filtering technique and semiconductor memory device having the same

A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Phase frequency detector capable of improving noise characteristics

The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.

Low divide ratio programmable frequency divider and method thereof

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Seoul, South Korea

Sung Cheol Shin