Micron Technology Incorporated

Motorola Corporation

Micron Semiconductor, Inc.

Sung C Kim

Scott G Meikle

Gurtej S Sandhu

Rajeev Bajaj

Daniel A Koos

Kirk D Prall

Guy T Blalock

Lei Ping Lai

Trung Tri Doan

Donald L Westmoreland

Chris C Yu

Janos Farkas

David J Kubista

Mark A Zaleski

Adam Manzonie

Jaime A Saravia

A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate, forming a layer of titanium/aluminum alloy on the surface of the substrate, and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Semiconductor structure with a titanium aluminum nitride layer and method for fabricating same

A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.

Semiconductor structure having interconnects on a projecting region and substrate

A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate forming a layer of titanium/aluminum alloy on the surface of the substrate and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Method of chemical mechanical polishing

A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate, forming a layer of titanium/aluminum alloy on the surface of the substrate and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Semiconductor structure with a titanium aluminum nitride layer and method for fabricating the same

A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (,) and a titanium layer (,) of a semiconductor device substrate (,) are polished using one polisher (,) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (,) from two different urce containers (,and,), wherein the first slurry is dispensed until e tungsten is removed and then the slurry dispense is switched to second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Processing for polishing dissimilar conductive layers in a semiconductor device

A process for conditioning a polishing pad has been developed that incorporates in-situ conditioning where the conditioning is performed while the substrate (27, 40) is on the polishing pad (22) but terminates before the polishing of the substrate (27, 40) is completed. In one embodiment, ex-situ conditioning of the polishing pad (22) is used on the polishing pad between substrates (27, 40). The process has benefits of both in-situ and ex-situ conditioning.

Process for forming a semiconductor device

Method for reducing the heights of interconnects on a projecting region

A polishing pad (34) with a poromeric structure polishes two dissimilar materials (56, 58). By using a relatively softer pad. and conditioning, relatively constant times can be used for polishing the dissimilar materials (56, 58). This makes polishing more predictable and increases the number of substrates that can be polished using a single polishing pad (34). Polishing pads (34) are typically changed when other maintenance is performed on the polisher rather than when the polishing rate becomes too low.

Process for polishing a semiconductor device substrate

A chemical mechanical polishing (CMP) method utilizes a polishing pad (21) and an under pad (20). The under pad (20) has an edge portion (24) and a central portion (22). The central portion (22) has either a shore D hardness less than a shore D hardness of the portion (24), greater slurry absorption than the edge portion (24), or more compressibility than the edge portion (24). This composite material under pad (20) will improve polishing uniformity of a semiconductor wafer (39). In addition, the use of the polishing pads (20 and 21) allows for greater final wafer profile control than was previously available in the art (FIGS. 4-6).

Method of chemical mechanical polishing (CMP) using an underpad with

A method of sputtering material onto semiconductor wafers includes: a) providing a sputtering chamber with a sputtering target, a wafer supporting chuck having a supported first wafer, and a collimator positioned between the target and first wafer for filtering material sputtered from the target onto the first wafer; b) providing ionized sputtering atoms within the chamber; c) bombarding the target with the ionized sputtering atoms to dislodge target atoms; d) passing the dislodged target atoms through collimator openings and onto the first wafer, the dislodged target atoms coating the collimator and openings passing therethrough; e) removing the sputter deposited first wafer from the sputtering chamber without breaking vacuum; f) after removing the sputtered first wafer, cleaning the collimator within the chamber without breaking vacuum between removal of the first wafer and the cleaning of the collimator within the chamber; and g) after cleaning of the collimator within the chamber, providing a second wafer on the wafer supporting chuck within the chamber without breaking vacuum between the cleaning of the collimator and the providing of the second wafer in the chamber; and thereafter sputter depositing target atoms onto the second wafer. The cleaning comprises providing the collimator with a negative potential effective to attract bombarding ionized sputtering atoms to dislodgingly clean target atoms from the collimator. The cleaning is to a degree sufficient to render collimator service lifetime at least equal to that of the sputtering target. Other cleaning techniques are disclosed.

Sputtering with collinator cleaning within the sputtering chamber

In semiconductor manufacture a method of shaping the features of a semiconductor structure using chemical mechanical planarization (CMP) is provided. During CMP, a relatively soft polishing pad is utilized to conform to and contour a topography of the semiconductor structure. Another layer of a material such as a dielectric (e.g. TEOS based silicon dioxide) can then be deposited over the contoured topography without the inclusion of voids. The method of the invention is particularly suited to the formation of void free dielectric layers.

Method for shaping features of a semiconductor structure using chemical

A process for depositing a thin film of aluminum nitride (AlN) includes sputtering an aluminum target with energetic nitrogen ions generated in a nitrogen plasma. A single gas (i.e. nitrogen) is used as both the reactive gas and as the sputtering gas. The process is especially adapted for forming an etchstop layer for use in forming contact vias through a dielectric layer in semiconductor manufacture. The process is also useful in semiconductor manufacture for forming an aluminum nitride (AlN) film that may be used as a passivation layer, as a ceramic packaging material, as a mask for ion implantation, as a substrate material in hybrid circuits, and as a high bandgap window for GaAs solar cells.

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Pflugerville, TX, United States of America

Sung C Kim