United Microelectronics Corp.

Sung-Bin Lin

Yen-Ting Ho

Wen-Chung Chang

Yuan-Hsiang Chang

Chien-Hung Chen

Tzyh-Cheang Lee

Shui-Chin Huang

Nai-Chen Peng

Yu-Huang Yeh

Ya-Huei Huang

Feng-Ji Tsai

Cherng-En Sun

Che-Lieh Lin

Chuan Fu Wang

A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

Semiconductor memory device and manufacturing method thereof

A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Trapping gate forming process and flash cell

A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

Structure of memory cell with asymmetric cell structure and method for fabricating the same

A method for fabricating memory device is disclosed. The method includes the steps of: providing a substrate having a tunnel oxide layer on the substrate, a first electrode layer on the tunnel oxide layer, an oxide-nitride-oxide (ONO) stack on the first electrode layer, and a second electrode layer on the ONO stack, and then removing part of the second electrode layer, part of the ONO stack, and part of the first electrode layer so that the tunnel oxide layer is not exposed.

Memory device and method for fabricating the same

A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a first gate conductive layer onto the substrate; forming a MOS transistor gate by executing a photolithography process on the first gate conductive layer, and then forming an ONO structure on the substrate; and forming a second gate conductive layer on the ONO substrate, and then forming a NVM transistor gate by executing a photolithography process on the second gate conductive layer.

Method of manufacturing non-volatile memory having SONOS memory cells

An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.

Operating method of memory device

A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.

Memory cell structure and method for forming the same

A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.

Method of making semiconductor device

Semiconductor device

A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region.

Non-volatile memory

A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency.

Structure and fabrication method of flash memory

The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first Pdoped drain region and a first Pdoped source region. The second PMOS transistor includes a gate and a second Pdoped source region. The first Pdoped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a Ndoped region. The floating gate overlaps with the N-well and extends to the Ndoped region. The overlapped region of the P-well and the Ndoped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Growing community of inventors

Hsinchu, Taiwan

Sung-Bin Lin