International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Infineon Technologies North America Corp.

Infineon Ag

Sunfei Fang

Zhijiong Luo

Cyril Cabral, Jr

Thomas W Dyer

Christian Lavoie

Clement Hsingjen Wann

Chester T Dziobkowski

Huilong Zhu

Brian Joseph Greene

Jiang Yan

Rajarao Jammy

Lawrence Alfred Clevenger

John J Ellis-Monaghan

Dureseti Chidambarrao

James Spiros Nakos

Jun Yuan

Yue Liang

Xiaojun Yu

An L Steegen

Ja-Hum Ku

Hung Y Ng

Jun Jung Kim

Effendi Leobandung

Ghavam G Shahidi

Haining S Yang

Vijay Narayanan

Balasubramanian Pranatharthiharan

Xiangdong Chen

Qingqing Liang

Renee Tong Mo

Terry Allen Spooner

Evgeni Petrovich Gousev

Vamsi Krishna Paruchuri

Chun-Yung Sung

Mahadevaiyer Krishnan

Nivo Rovedo

Jay William Strane

Yong Meng Lee

Edward P Maciejewski

Yanfeng Wang

Randolph F Knarr

Michelle Leigh Steen

Patrick William Dehaven

Johnny Widodo

Kevin K Dezfulian

Scott D Allen

Jun-jung Kim

O-sung Kwon

Chih-Chao Yang

Oleg Gluschenkov

Yun Yu Wang

Keith Kwong Hon Wong

Judson Robert Holt

Timothy Joseph Dalton

Haizhou Yin

Fei Liu

Qing Cao

Zhen Zhang

Andrew Herbert Simon

Zhengwen O Li

Stephen Edward Greco

Kwong Hon Wong

Byeong Yeol Kim

Kaushik Chanda

Manfred Eller

Rishikesh Krishnan

Alois Gutmann

Paul David Agnello

Siddhartha Panda

Sang-Jine Park

Min-ho Lee

Mahender Kumar

Yaocheng Liu

Young Way Teh

Daewon Yang

Jakub Tadeusz Kedzierski

Larry Clevenger

Andy Cowley

Hasan Munir Nayfeh

Richard J Murphy

Jae-eon Park

Tsong-Lin Tai

Min-chul Sun

Hsiang-Jen Huang

Dae-won Yang

Wee Lang Tan

Chin-Chao Yang

JunJung Kim

Renee T c/o Ibm United Kingdom Limited Mo

Christian c/o Ibm United Kingdom Limited Lavoie

Jay W Strane

In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1&#xd7;10ohm-cmto about 1&#xd7;10ohm-cm; a dielectric in the trench covering the bottom electrode; and a top electrode in the trench separated from the bottom electrode by the dielectric.

Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal process

A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600&#xb0; C. or less.

Shallow trench isolation for device including deep trench capacitors

A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500&#xb0; C.) nitridation process.

Structure and method to improve threshold voltage of MOSFETs including a high k dielectric

A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.

A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500&#xb0; C.) nitridation process.

Structure and method to improve threshold voltage of MOSFETS including a high K dielectric

The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Method for forming self-aligned metal silicide contacts

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors

A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.

Asymmetric semiconductor devices and method of fabricating

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Forming conductive stud for semiconductive devices

A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

Field effect transistors (FETs) with multiple and/or staircase silicide

A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200&#xb0; C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Dual stress memory technique method and related structure

An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Formation of fully silicided metal gate using dual self-aligned silicide process

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Lagrangeville, NY, United States of America

Sunfei Fang