Intel Corporation

Suneeta Sah

Kuljit Singh Bains

John H Crawford

George Vergis

Brian S Morris

James A McCall

Bill Nale

Pete D Vogt

Christopher E Cox

Howard S David

Sivakumar Radhakrishnan

Sreenivas Mandava

John R Goles

Chong J Zhao

Roy M Stevens

Klaus J Ruff

Ted Rossin

Mathew W Stefaniw

John B Halbert

Rajat Agarwal

Eugene Gorbatov

Ulf Hanebutte

James W Alexander

Zvika Greenfield

Sin Sim Tan

Stanley Steve Kulick

Suresh S Chittor

William Harry Nale

Prantik K Nag

Chitra Natarajan

Siva Balasubramanian

Rami A Naqib

Varin Udompanyanan

Joseph Ku

Hrishikesh S Pai

Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Techniques to access or operate a dual in-line memory module via multiple data channels

A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

Mapping a physical address differently to different memory devices in a group

Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed.

Refresh parameter-dependent memory refresh management

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Techniques for determining victim row addresses in a volatile memory

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Accessing data stored in a command/address register device

Memory refresh management

Embodiments of apparatus, methods, systems, computer-readable storage media and devices are described herein for determining an error category for a detected error in data read from a volatile memory; and selectively performing or causing an additional remedial action based at least in part on the error category determined. In various embodiments, the determining and the performing or causing may be undertaken in response to the correcting. The memory may be volatile or non-volatile memory. Other embodiments may be described and/or claimed.

Selective remedial action based on category of detected error for a memory read

A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

Method, apparatus and system for providing a memory refresh

Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.

Memory power management via dynamic memory operation states

In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Power management using adaptive thermal throttling

Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

Maximal length packets

Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Memory read/write reordering

Growing community of inventors

Portland, OR, United States of America

Suneeta Sah